Providing transposable access to a synapse array using a recursive array layout
Barth, Jr., John E, Merolla, Paul A, Arthur, John V, Modha, Dharmendra S
Year of Publication 27.07.2021
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Year of Publication 27.07.2021
Patent
BLOCK TRANSFER OF NEURON OUTPUT VALUES THROUGH DATA MEMORY FOR NEUROSYNAPTIC PROCESSORS
MODHA, Dharmendra, ARTHUR, John, ESSER, Steven, SAWADA, Jun, DATTA, Pallab
Year of Publication 03.10.2019
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Year of Publication 03.10.2019
Patent
Hardware architecture for simulating a neural network of neurons
Cassidy, Andrew S, Merolla, Paul A, Arthur, John V, Alvarez-Icaza Rivera, Rodrigo, Modha, Dharmendra S, Datta, Pallab
Year of Publication 24.05.2022
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Year of Publication 24.05.2022
Patent
NEURAL NETWORK PROCESSING
ARTHUR, JOHN VERNON, APPUSWAMY, RATHINAKUMAR, CASSIDY, ANDREW STEPHEN, DATTA, PALLAB, NAYAK, TAPAN KUMAR, DEBOLE, MICHAEL VINCENT, SAWADA, JUN, MODHA, DHARMENDRA
Year of Publication 28.04.2022
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Year of Publication 28.04.2022
Patent
RUNTIME RECONFIGURABLE NEURAL NETWORK PROCESSOR CORE
Flickner, Myron D, Esser, Steven K, Sawada, Jun, Penner, Hartmut, Appuswamy, Rathinakumar, Klamo, Jennifer, Cassidy, Andrew S, Arthur, John V, Taba, Brian, Modha, Dharmendra S, Datta, Pallab
Year of Publication 02.03.2023
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Year of Publication 02.03.2023
Patent
Art of constructing low-complexity encoders/decoders for constrained block codes
Modha, D.S., Marcus, B.H.
Published in IEEE journal on selected areas in communications (01.04.2001)
Published in IEEE journal on selected areas in communications (01.04.2001)
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Journal Article