A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
Published in IEEE journal of solid-state circuits (01.01.2010)
Published in IEEE journal of solid-state circuits (01.01.2010)
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Conference Proceeding
PREPARATION OF CHLOROACETALDEHYDE CYCLIC TRIMER AND ITS DEPOLYMERIZATION
WAKASUGI, T, TONOUCHI, N, MIYAKAWA, T, ISHIZUKA, M, YAMAUCHI, T, ITSUNO, S, ITO, K
Published in Chemistry letters (01.01.1992)
Published in Chemistry letters (01.01.1992)
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A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
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A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs
Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.
Published in IEEE journal of solid-state circuits (01.09.2011)
Published in IEEE journal of solid-state circuits (01.09.2011)
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