Linking EUV lithography line edge roughness and 16 nm NAND memory performance
VAGLIO PRET, Alessandro, POLIAKOV, Pavel, GRONHEID, Roel, BLOMME, Pieter, CORBALAN, Miguel Miranda, DEHAENE, Wim, VERKEST, Diederik, VAN HOUDT, Jan, BIANCHI, Davide
Published in Microelectronic engineering (01.10.2012)
Published in Microelectronic engineering (01.10.2012)
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Journal Article
Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash Arrays
Poliakov, P., Blomme, P., Pret, A. V., Corbalan, M. M., Gronheid, R., Verkest, D., Van Houdt, J., Dehaene, W.
Published in IEEE electron device letters (01.02.2012)
Published in IEEE electron device letters (01.02.2012)
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Journal Article
3차원 PDN(Power Distribution Network) 커패시터 통합
KHAN IRFAN, PANDEY SHREE KRISHNA, MIRANDA CORBALAN MIGUEL, SONG STANLEY SEUNGCHUL, XIE BIANCUN
Year of Publication 12.01.2024
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Year of Publication 12.01.2024
Patent
Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories
Poliakov, Pavel, Blomme, Pieter, Pret, Alessandro Vaglio, Corbalan, Miguel Miranda, Gronheid, Roel, Verkest, Diederik, Houdt, Jan Van, Dehaene, Wim
Published in Microelectronics and reliability (01.03.2012)
Published in Microelectronics and reliability (01.03.2012)
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Journal Article
Linking EUV lithography line edge roughness and 16nm NAND memory performance
Vaglio Pret, Alessandro, Poliakov, Pavel, Gronheid, Roel, Blomme, Pieter, Miranda Corbalan, Miguel, Dehaene, Wim, Verkest, Diederik, Van Houdt, Jan, Bianchi, Davide
Published in Microelectronic engineering (01.10.2012)
Published in Microelectronic engineering (01.10.2012)
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Journal Article
Linking EUV lithography line edge roughness and 16ANBnm NAND memory performance
Vaglio Pret, Alessandro, Poliakov, Pavel, Gronheid, Roel, Blomme, Pieter, Miranda Corbalan, Miguel, Dehaene, Wim, Verkest, Diederik, Van Houdt, Jan, Bianchi, Davide
Published in Microelectronic engineering (01.10.2012)
Published in Microelectronic engineering (01.10.2012)
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Journal Article
Power and signal integrity challenges in 3D systems
Corbalan, Miguel Miranda, Keval, Anup, Toms, Thomas, Lisk, Durodami, Radojcic, Riko, Nowak, Matt
Published in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29.05.2013)
Published in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29.05.2013)
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Conference Proceeding
STACKED INTEGRATED CIRCUIT DEVICE INCLUDING INTEGRATED CAPACITOR DEVICE
LI, Yue, POPOVIC, Darko, MIRANDA CORBALAN, Miguel, LISK, Durodami, KHAN, Irfan
Year of Publication 31.10.2024
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Year of Publication 31.10.2024
Patent
STACKED INTEGRATED CIRCUIT DEVICE INCLUDING INTEGRATED CAPACITOR DEVICE
LI, Yue, POPOVIC, Darko, MIRANDA CORBALAN, Miguel, LISK, Durodami, KHAN, Irfan
Year of Publication 31.10.2024
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Year of Publication 31.10.2024
Patent
THREE-DIMENSIONAL POWER DISTRIBUTION NETWORK (PDN) CAPACITOR INTEGRATION
XIE, Biancun, MIRANDA CORBALAN, Miguel, SONG, Stanley Seungchul, KHAN, Irfan, PANDEY, Shree Krishna
Year of Publication 06.03.2024
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Year of Publication 06.03.2024
Patent
THREE-DIMENSIONAL POWER DISTRIBUTION NETWORK (PDN) CAPACITOR INTEGRATION
XIE, Biancun, MIRANDA CORBALAN, Miguel, SONG, Stanley Seungchul, KHAN, Irfan, PANDEY, Shree Krishna
Year of Publication 03.11.2022
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Year of Publication 03.11.2022
Patent