13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique
Wei, Liqiong, Alzate, Juan G., Arslan, Umut, Brockman, Justin, Das, Nilanjan, Fischer, Kevin, Ghani, Tahir, Golonzka, Oleg, Hentges, Patrick, Jahan, Rawshan, Jain, Pulkit, Lin, Blake, Meterelliyoz, Mesut, OrDonnell, Jim, Puls, Conor, Quintero, Pedro, Sahu, Tanaya, Sekhar, Meenakshi, Vangapaty, Ajay, Wiegand, Chris, Hamzaoglu, Fatih
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology
Hamzaoglu, Fatih, Arslan, Umut, Bisnik, Nabhendra, Ghosh, Swaroop, Lal, Manoj B., Lindert, Nick, Meterelliyoz, Mesut, Osborne, Randy B., Joodong Park, Tomishima, Shigeki, Yih Wang, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.01.2015)
Published in IEEE journal of solid-state circuits (01.01.2015)
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Journal Article
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry
Karl, E., Yih Wang, Yong-Gee Ng, Zheng Guo, Hamzaoglu, F., Meterelliyoz, M., Keane, J., Bhattacharya, U., Zhang, K., Mistry, K., Bohr, M.
Published in IEEE journal of solid-state circuits (01.01.2013)
Published in IEEE journal of solid-state circuits (01.01.2013)
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Journal Article
Conference Proceeding
Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM
Yih Wang, Karl, E., Meterelliyoz, M., Hamzaoglu, F., Yong-Gee Ng, Ghosh, S., Liqiong Wei, Bhattacharya, U., Zhang, K.
Published in 2011 International Electron Devices Meeting (01.12.2011)
Published in 2011 International Electron Devices Meeting (01.12.2011)
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Conference Proceeding
13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V
Jain, Pulkit, Arslan, Umut, Sekhar, Meenakshi, Lin, Blake C., Wei, Liqiong, Sahu, Tanaya, Alzate-vinasco, Juan, Vangapaty, Ajay, Meterelliyoz, Mesut, Strutt, Nathan, Chen, Albert B., Hentges, Patrick, Quintero, Pedro A., Connor, Chris, Golonzka, Oleg, Fischer, Kevin, Hamzaoglu, Fatih
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor
Meterelliyoz, M, Song, P, Stellari, F, Kulkarni, J P, Roy, K
Published in IEEE transactions on circuits and systems. I, Regular papers (01.08.2010)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.08.2010)
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Journal Article
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits
Jung Hwan Choi, Bansal, A., Meterelliyoz, M., Murthy, J., Roy, K.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2007)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2007)
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Journal Article
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
Hamzaoglu, Fatih, Arslan, Umut, Bisnik, Nabhendra, Ghosh, Swaroop, Lal, Manoj B., Lindert, Nick, Meterelliyoz, Mesut, Osborne, Randy B., Joodong Park, Tomishima, Shigeki, Yih Wang, Zhang, Kevin
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
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Conference Proceeding
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost
Goel, A., Ghosh, S., Meterelliyoz, M., Parkhurst, J., Roy, K.
Published in 2011 Asian Test Symposium (01.11.2011)
Published in 2011 Asian Test Symposium (01.11.2011)
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Conference Proceeding
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit
Meterelliyoz, M., Goel, A., Kulkarni, J.P., Roy, K.
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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Conference Proceeding
Thermal analysis of 8-T SRAM for nano-scaled technologies
Meterelliyoz, Mesut, Kulkarni, Jaydeep P., Roy, Kaushik
Published in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) (11.08.2008)
Published in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) (11.08.2008)
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Conference Proceeding
A leakage control system for thermal stability during burn-in test
Meterelliyoz, M., Mahmoodi, H., Roy, K.
Published in IEEE International Conference on Test, 2005 (2005)
Published in IEEE International Conference on Test, 2005 (2005)
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Conference Proceeding
A high sensitivity process variation sensor utilizing sub-threshold operation
Meterelliyoz, M., Song, P., Stellari, F., Kulkarni, J.P., Roy, K.
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
Published in 2008 IEEE Custom Integrated Circuits Conference (01.09.2008)
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Conference Proceeding
High retention time memory element with dual gate devices
Meterelliyoz, Mesut, Le, Van H, Rios, Rafael, Kavalieros, Jack, Dewey, Gilbert
Year of Publication 29.12.2020
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Year of Publication 29.12.2020
Patent
HIGH RETENTION TIME MEMORY ELEMENT WITH DUAL GATE DEVICES
METERELLIYOZ, Mesut, RIOS, Rafael, DEWEY, Gilbert, LE, Van H, KAVALIEROS, Jack
Year of Publication 27.02.2020
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Year of Publication 27.02.2020
Patent
HIGH RETENTION TIME MEMORY ELEMENT WITH DUAL GATE DEVICES
METERELLIYOZ, Mesut, RIOS, Rafael, DEWEY, Gilbert, LE, Van, KAVALIEROS, Jack
Year of Publication 21.06.2018
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Year of Publication 21.06.2018
Patent
Retention time optimization for eDRAM in 22nm tri-gate CMOS technology
Yih Wang, Arslan, Umut, Bisnik, Nabhendra, Brain, Ruth, Ghosh, Swaroop, Hamzaoglu, Fatih, Lindert, Nick, Meterelliyoz, Mesut, Park, Joodong, Tomishima, Shigeki, Zhang, Kevin
Published in 2013 IEEE International Electron Devices Meeting (01.12.2013)
Published in 2013 IEEE International Electron Devices Meeting (01.12.2013)
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Conference Proceeding
Journal Article