Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures
Lambrechts, A., Raghavan, P., Jayapala, M., Bingfeng Mei, Catthoor, F., Verkest, D.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.01.2009)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.01.2009)
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Journal Article
Hardware and a Tool Chain for ADRES
De Sutter, Bjorn, Mei, Bingfeng, Bartic, Andrei, Aa, Tom Vander, Berekovic, Mladen, Mignolet, Jean-Yves, Croes, Kris, Coene, Paul, Cupac, Miro, Couvreur, Aïssa, Folens, Andy, Dupont, Steven, Van Thielen, Bert, Kanstein, Andreas, Kim, Hong-Seok, Kim, Suk Jin
Published in Lecture notes in computer science (2006)
Published in Lecture notes in computer science (2006)
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Book Chapter
Conference Proceeding
Architecture exploration for a reconfigurable architecture template
Mei, B., Lambrechts, A., Mignolet, J.-Y., Verkest, D., Lauwereins, R.
Published in IEEE design & test of computers (01.03.2005)
Published in IEEE design & test of computers (01.03.2005)
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Journal Article
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
Wilton, S.J.E., Kafafi, N., Bingfeng Mei, Vernalde, S.
Published in Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) (2004)
Published in Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) (2004)
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Conference Proceeding
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
Berekovic, Mladen, Kanstein, Andreas, Mei, Bingfeng, Sutter, Bjorn De
Published in Microprocessors and microsystems (01.06.2009)
Published in Microprocessors and microsystems (01.06.2009)
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Journal Article
Design style case study for embedded multi media compute nodes
Lambrechts, A., Aa, T.V., Jayapala, M., Talavera, G., Leroy, A., Shickova, A., Barat, F., Bingfeng Mei, Catthoor, F., Verkest, D., Deconinck, G., Corporaal, H., Robert, F., Bordoll, J.C.
Published in 25th IEEE International Real-Time Systems Symposium (2004)
Published in 25th IEEE International Real-Time Systems Symposium (2004)
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Conference Proceeding
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
Mei, Bingfeng, Vernalde, Serge, Verkest, Diederik, De Man, Hugo, Lauwereins, Rudy
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03.03.2003)
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03.03.2003)
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Conference Proceeding