Search Results - "MASON, JEFFREY M" :: K.UTB vyhledávací portál

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Processor and cache arrangement with selective caching between first-level and second-level caches

by MASON JEFFREY M, BENNETT DAVID W
Year of Publication 21.10.2014

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Secure cloud computing infrastructure

by MASON JEFFREY M, BENNETT DAVID W
Year of Publication 16.09.2014

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Compiler directed cache coherence for many caches generated from high-level language source code

by MASON JEFFREY M, PUTNAM ANDREW R, SUNDARARAJAN PRASANNA
Year of Publication 28.06.2016

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Floating-point processing unit for successive floating-point operations

by MASON JEFFREY M, BENNETT DAVID W
Year of Publication 29.03.2011

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Floating-point processing unit for successive floating-point operations

by Mason, Jeffrey M, Bennett, David W
Year of Publication 29.03.2011

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Method and apparatus for providing secure intellectual property cores for a programmable logic device

by MASON JEFFREY M, YOUNG JAY T
Year of Publication 15.02.2011

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Method and apparatus for providing secure intellectual property cores for a programmable logic device

by Young, Jay T, Mason, Jeffrey M
Year of Publication 15.02.2011

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Determining sizes of FIFO buffers between functional blocks in an electronic circuit

by MASON JEFFREY M, BENNETT DAVID W
Year of Publication 19.10.2010

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Determining sizes of FIFO buffers between functional blocks in an electronic circuit

by Bennett, David W, Mason, Jeffrey M
Year of Publication 19.10.2010

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Versatile bus interface macro for dynamically reconfigurable designs

by Mason, Jeffrey M, Leavesley, III, W. Story
Year of Publication 17.11.2009

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Versatile bus interface macro for dynamically reconfigurable designs

by MASON JEFFREY M, LEAVESLEY, III W. STORY
Year of Publication 17.11.2009

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Method and apparatus for modular circuit design for a programmable logic device

by MASON JEFFREY M, YOUNG JAY T
Year of Publication 06.10.2009

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Method and apparatus for modular circuit design for a programmable logic device

by Mason, Jeffrey M, Young, Jay T
Year of Publication 06.10.2009

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Versatile bus interface macro for dynamically reconfigurable designs

by Mason, Jeffrey M, Leavesley, III, W. Story
Year of Publication 13.01.2009

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Versatile bus interface macro for dynamically reconfigurable designs

by MASON JEFFREY M, LEAVESLEY, III W. STORY
Year of Publication 13.01.2009

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Generation of cache architecture from a high-level language description

by MASON JEFFREY M, WENZL LAUREN B, BENNETT DAVID W, DIMOND ROBERT G, SUNDARARAJAN PRASANNA
Year of Publication 25.06.2013

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MODULAR DESIGN METHOD AND SYSTEM FOR PROGRAMMABLE LOGIC DEVICES

by TALLEY, BRUCE E, MASON, JEFFREY M, LASS, STEVE E, BENNETT, DAVID W
Year of Publication 02.04.2013

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Methods for automatically generating fault mitigation strategies for electronic system designs

by MASON JEFFREY M, BENNETT DAVID W, CORBETT JOHN D, SUNDARARAJAN PRASANNA
Year of Publication 19.04.2011

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Methods for automatically generating fault mitigation strategies for electronic system designs

by Sundararajan, Prasanna, Corbett, John D, Bennett, David W, Mason, Jeffrey M
Year of Publication 19.04.2011

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Incremental design using a group area designation

by Barras, Arne S, Mason, Jeffrey M, Kelley, Kate L
Year of Publication 01.08.2006

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