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Year of Publication 28.12.2016
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Year of Publication 01.10.2019
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Method to do control speculation on loads in a high performance strand-based loop accelerator
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Year of Publication 26.03.2019
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Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator
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Year of Publication 26.03.2019
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Year of Publication 26.03.2019
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Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor
Ostanevich, Alexander Y, Ermolovich, Alexander V, Rozhkov, Sergey A, Scherbinin, Sergey P, Motin, Denis G, Maslennikov, Dmitry M, Chudnovets, Andrey, Iyer, Jayesh, Babayan, Boris A
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Year of Publication 19.03.2019
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METHOD TO DO CONTROL SPECULATION ON LOADS IN A HIGH PERFORMANCE STRAND-BASED LOOP ACCELERATOR
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Year of Publication 28.06.2018
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Year of Publication 28.06.2018
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METHOD AND APPARATUS TO CREATE REGISTER WINDOWS FOR PARALLEL ITERATIONS TO ACHIEVE HIGH PERFORMANCE IN HW-SW CODESIGNED LOOP ACCELERATOR
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Year of Publication 28.06.2018
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Year of Publication 28.06.2018
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METHOD AND APPARATUS TO EFFICIENTLY HANDLE ALLOCATION OF MEMORY ORDERING BUFFERS IN A MULTI-STRAND OUT-OF-ORDER LOOP PROCESSOR
CHUDNOVETS, Andrey, OSTANEVICH, Alexander Y, BABAYAN, Boris A, SCHERBININ, Sergey P, MASLENNIKOV, Dmitry M, ROZHKOV, Sergey A, MOTIN, Denis G, IYER, Jayesh, ERMOLOVICH, Alexander V
Year of Publication 28.06.2018
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Year of Publication 28.06.2018
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METHOD AND APPARATUS TO CREATE REGISTER WINDOWS FOR PARALLEL ITERATIONS TO ACHIEVE HIGH PERFORMANCE IN HW-SW CODESIGNED LOOP ACCELERATOR
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Year of Publication 27.06.2018
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Year of Publication 27.06.2018
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INCREASING PROCESSOR INSTRUCTION WINDOW VIA SEPERATING INSTRUCTIONS ACCORDING TO CRITICALITY
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Year of Publication 08.06.2017
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Year of Publication 08.06.2017
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Systems, methods, and apparatuses for improving performance of status dependent computations
MATVEYEV, PAVEL G, CAPRIOLI, PAUL, MASLENNIKOV, DMITRY M, HABER, GADI
Year of Publication 01.04.2017
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Year of Publication 01.04.2017
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METHODS AND APPARATUS TO COMPILE INSTRUCTIONS FOR A VECTOR OF INSTRUCTION POINTERS PROCESSOR ARCHITECTURE
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Year of Publication 12.11.2015
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Year of Publication 12.11.2015
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Systeme, Verfahren und Vorrichtungen zur Leistungsverbesserung von statusabhängigen Berechnungen
Haber, Gadi, Matveyev, Pavel G, Maslennikov, Dmitry M, Caprioli, Paul
Year of Publication 29.12.2016
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Year of Publication 29.12.2016
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Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture
MASLENNIKOV DMITRY M, RODCHENKO ANDREY, MATVEYEV PAVEL G, SHURYGIN BORIS V, SCHERBININ SERGEY P, CHUDNOVETS ANDREY, ZAKIROV MARAT, ASTIGEYEVICH YEVGENIY M
Year of Publication 21.07.2015
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Year of Publication 21.07.2015
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METHODS AND APPARATUS TO COMPILE INSTRUCTIONS FOR A VECTOR OF INSTRUCTION POINTERS PROCESSOR ARCHITECTURE
MASLENNIKOV DMITRY M, RODCHENKO ANDREY, MATVEYEV PAVEL G, SHURYGIN BORIS V, SCHERBININ SERGEY P, CHUDNOVETS ANDREY, ZAKIROV MARAT, ASTIGEYEVICH YEVGENIY M
Year of Publication 18.09.2014
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Year of Publication 18.09.2014
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