Completely verifying memory consistency of test program executions
Manovit, C., Hangal, S.
Published in The Twelfth International Symposium on High-Performance Computer Architecture, 2006 (2006)
Published in The Twelfth International Symposium on High-Performance Computer Architecture, 2006 (2006)
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Conference Proceeding
Testing implementations of transactional memory
Manovit, Chaiyasit, Hangal, Sudheendra, Chafi, Hassan, McDonald, Austen, Kozyrakis, Christos, Olukotun, Kunle
Published in 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2006)
Published in 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2006)
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Conference Proceeding
Method and apparatus for verifying output-based clock gating
NARAYANAN SRIDHAR, SUBRAMANIAN SRIDHAR, MANOVIT CHAIYASIT, KUCHLOUS ALOK, CAO WANLIN
Year of Publication 16.04.2013
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Year of Publication 16.04.2013
Patent
Method for clock gating circuits
Manovit, Chaiyasit, Cao, Wanlin, Narayanan, Sridhar, Subramanian, Sridhar
Year of Publication 10.07.2012
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Year of Publication 10.07.2012
Patent
Method for clock gating circuits
NARAYANAN SRIDHAR, SUBRAMANIAN SRIDHAR, MANOVIT CHAIYASIT, CAO WANLIN
Year of Publication 10.07.2012
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Year of Publication 10.07.2012
Patent