The Low Area Probing Detector as a Countermeasure Against Invasive Attacks
Weiner, Michael, Manich, Salvador, Rodriguez-Montanes, Rosa, Sigl, Georg
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2018)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2018)
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A Calibratable Detector for Invasive Attacks
Weiner, Michael, Wieser, Wolfgang, Lupon, Emili, Sigl, Georg, Manich, Salvador
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2019)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2019)
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Unpredictable Bits Generation Based on RRAM Parallel Configuration
Arumi, Daniel, Gomez-Pau, Alvaro, Manich, Salvador, Rodriguez-Montanes, Rosa, Gonzalez, Mireia Bargallo, Campabadal, Francesca
Published in IEEE electron device letters (01.02.2019)
Published in IEEE electron device letters (01.02.2019)
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A Highly Time Sensitive XOR Gate for Probe Attempt Detectors
Manich, Salvador, Strasser, Martin
Published in IEEE transactions on circuits and systems. II, Express briefs (01.11.2013)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.11.2013)
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Impact of Laser Attacks on the Switching Behavior of RRAM Devices
Arumí, Daniel, Manich, Salvador, Gómez-Pau, Álvaro, Rodríguez-Montañés, Rosa, Montilla, Víctor, Hernández, David, González, Mireia Bargalló, Campabadal, Francesca
Published in Electronics (Basel) (01.01.2020)
Published in Electronics (Basel) (01.01.2020)
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Improving security in cache memory by power efficient scrambling technique
Neagu, Mădălin-Ioan, Miclea, Liviu, Manich, Salvador
Published in Chronic diseases and translational medicine (01.11.2015)
Published in Chronic diseases and translational medicine (01.11.2015)
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Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis
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Differential scan-path: A novel solution for secure design-for-testability
Manich, S., Wamser, Markus S., Guillen, Oscar M., Sigl, G.
Published in 2013 IEEE International Test Conference (ITC) (01.09.2013)
Published in 2013 IEEE International Test Conference (ITC) (01.09.2013)
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Conference Proceeding
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Design and validation of a platform for electromagnetic fault injection
Balasch, Josep, Arumi, Daniel, Manich, Salvador
Published in 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2017)
Published in 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2017)
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Conference Proceeding
Defeating Simple Power Analysis attacks in cache memories
Neagu, Madalin, Miclea, Liviu, Manich, Salvador
Published in 2015 Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2015)
Published in 2015 Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2015)
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Conference Proceeding
RRAM based cell for hardware security applications
Arumi, Daniel, Manich, Salvador, Rodriguez-Montanes, Rosa
Published in 2016 1st IEEE International Verification and Security Workshop (IVSW) (01.07.2016)
Published in 2016 1st IEEE International Verification and Security Workshop (IVSW) (01.07.2016)
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Conference Proceeding
RRAM based random bit generation for hardware security applications
Arumi, Daniel, Manich, Salvador, Rodriguez-Montanes, Rosa, Pehl, Michael
Published in 2016 Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2016)
Published in 2016 Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2016)
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Conference Proceeding
Crypto-Test-Lab for security validation of ECC co-processor test infrastructure
Lupon, Emili, Rodriguez-Montanes, Rosa, Manich, Salvador
Published in 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2017)
Published in 2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) (01.11.2017)
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Conference Proceeding
Interleaved scrambling technique: A novel low-power security layer for cache memories
Neagu, Madalin, Miclea, Liviu, Manich, Salvador
Published in 2014 19th IEEE European Test Symposium (ETS) (01.05.2014)
Published in 2014 19th IEEE European Test Symposium (ETS) (01.05.2014)
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Conference Proceeding
Defective Behaviour of an 8T SRAM Cell with Open Defects
Rodríguez-Montañés, R, Arumí, D, Manich, S, Figueras, J, Di Carlo, S, Prinetto, P, Scionti, A
Published in 2010 Second International Conference on Advances in System Testing and Validation Lifecycle (01.08.2010)
Published in 2010 Second International Conference on Advances in System Testing and Validation Lifecycle (01.08.2010)
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