Search Results - "MANEPALLI, Rahul N" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING

EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING

by MAY ROBERT ALAN, PIETAMBARAM SRINIVAS VENKATA RAMANUJA, MANEPALLI RAHUL N, PENMECHA BHARAT P, SANKMAN ROBERT L
Year of Publication 07.10.2021

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INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES

INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES

by IBRAHIM TAREK, MANEPALLI RAHUL N, PIETAMBARAM SRINIVAS V, DARMAWIKARTA KRISTOF, MALLIK DEBENDRA, SANKMAN ROBERT L
Year of Publication 07.10.2020

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상이한 두께들을 갖는 내장 다이들을 수용하는 패치

상이한 두께들을 갖는 내장 다이들을 수용하는 패치

by MAY ROBERT ALAN, PIETAMBARAM SRINIVAS, MANEPALLI RAHUL N, BOYAPATI SRI RANGA SAI, TANAKA HIROKI, DARMAWIKARTA KRISTOF
Year of Publication 07.08.2020

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고대역폭 광학 상호연결 아키텍처들

고대역폭 광학 상호연결 아키텍처들

by PRATAP DIVYA, POTHUKUCHI SURESH V, MANSURI MOZHGAN, AYGUN KEMAL, LI XIAOQIAN, SARKAR ARNAB, PAITAL SAMEER, DARMAWIKARTA KRISTOF, BROWN KENNETH, ZHANG ZHICHAO, INTI RAJESH, JADHAV SUSHEEL, ECTON JEREMY, DUAN GANG, KARHADE OMKAR, MAHAJAN RAVINDRANATH V, VADLIMANI SAI, MANEPALLI RAHUL N, MARIN BRANDON C, JAUSSI JAMES E, DESHPANDE NITIN, CASPER BRYAN K, NIE BAI, DOBRIYAL PRIYANKA, AGRAWAL ANKAR, SHARAN SUJIT, PIETAMBARAM SRINIVAS V, MALLIK DEBENDRA, GAMBA JASON M
Year of Publication 07.07.2023

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MICROELECTRONIC PACKAGES AND MICROELECTRONIC PACKAGING METHODS FOR IMPROVING LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

MICROELECTRONIC PACKAGES AND MICROELECTRONIC PACKAGING METHODS FOR IMPROVING LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

by OKA MIHIR A, KANAOKA YOSUKE, XU DINGYING, MANEPALLI RAHUL N, VORONOV SERGEI L, SUN DONG HAI
Year of Publication 15.03.2018

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Patent

METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

by OKA MIHIR A, KANAOKA YOSUKE, XU DINGYING, MANEPALLI RAHUL N, VORONOV SERGEI L, SUN DONG HAI
Year of Publication 18.01.2017

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Patent

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA(TSV) DIE EMBEDDED IN PACKAGE

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA(TSV) DIE EMBEDDED IN PACKAGE

by RAORANE DIGVIJAY A, LI YONGGANG, SOTO GONZALEZ JAVIER, MANEPALLI RAHUL N
Year of Publication 21.11.2014

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Patent

METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES

by OKA MIHIR A, KANAOKA YOSUKE, XU DINGYING, MANEPALLI RAHUL N, VORONOV SERGEI L, SUN DONG HAI
Year of Publication 01.07.2014

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Patent

MICROELECTRONIC1 PACKAGES WITH EMBEDDED INTERPOSERS

MICROELECTRONIC1 PACKAGES WITH EMBEDDED INTERPOSERS

by AZIMI, Hamid, MANEPALLI, Rahul N
Year of Publication 31.07.2024

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Patent

MICROELECTRONIC PACKAGES WITH EMBEDDED INTERPOSERS

MICROELECTRONIC PACKAGES WITH EMBEDDED INTERPOSERS

by Azimi, Hamid, Manepalli, Rahul N
Year of Publication 30.03.2023

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Patent

MICROELECTRONIC1 PACKAGES WITH EMBEDDED INTERPOSERS

MICROELECTRONIC1 PACKAGES WITH EMBEDDED INTERPOSERS

by AZIMI, Hamid, MANEPALLI, Rahul N
Year of Publication 30.03.2023

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Patent

ELECTRICAL INTERCONNECT BRIDGE

ELECTRICAL INTERCONNECT BRIDGE

by PIETAMBARAM, Srinivas V, MANEPALLI, Rahul N
Year of Publication 09.11.2023

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Electrical interconnect bridge

Electrical interconnect bridge

by Pietambaram, Srinivas V, Manepalli, Rahul N
Year of Publication 17.10.2023

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Semiconductor package having polymeric interlayer disposed between conductive elements and dielectric layer

Semiconductor package having polymeric interlayer disposed between conductive elements and dielectric layer

by Nad, Suddhasattwa, Manepalli, Rahul N
Year of Publication 22.02.2022

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Molded embedded bridge including routing layers for enhanced EMIB applications

Molded embedded bridge including routing layers for enhanced EMIB applications

by Pietambaram, Srinivas Venkata Ramanuja, Manepalli, Rahul N
Year of Publication 07.03.2023

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MULTI-LAYER MOLDED SUBSTRATE WITH GRADED CTE

MULTI-LAYER MOLDED SUBSTRATE WITH GRADED CTE

by Pietambaram, Srinivas V, Manepalli, Rahul N
Year of Publication 17.08.2022

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Patent

Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches

Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches

by Feng, Hongxia, Guo, Xiaoying, Han, Jung Kyu, Manepalli, Rahul N
Year of Publication 09.04.2024

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Patent

SEMICONDUCTOR PACKAGE AND METHOD OF MAKING

SEMICONDUCTOR PACKAGE AND METHOD OF MAKING

by Nad, Suddhasattwa, Manepalli, Rahul N
Year of Publication 27.08.2020

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Patent

Multi-layer molded substrate with graded CTE

Multi-layer molded substrate with graded CTE

by Pietambaram, Srinivas, Manepalli, Rahul N
Year of Publication 02.06.2020

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MOAT PROTECTION TO PREVENT CRACK PROPAGATION IN GLASS CORE SUBSTRATES OR GLASS INTERPOSERS

MOAT PROTECTION TO PREVENT CRACK PROPAGATION IN GLASS CORE SUBSTRATES OR GLASS INTERPOSERS

by TANIKELLA, Ravindra, PIETAMBARAM, Srinivas V, MANEPALLI, Rahul N
Year of Publication 23.03.2023

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