Showing
1 - 20
results of
61
for search '
"Low Yip Seng"
'
Skip to content
Portal K.UTB
Čeština
Login
TBU Catalog
e-resources
E-THESES
All Fields
Title
Author
Subject
Find
Advanced Search
Search Results - "Low Yip Seng"
Showing
1 - 20
results of
61
for search '
"Low Yip Seng"
'
, query time: 1.00s
Refine Results
Sort
Relevance
Date Descending
Date Ascending
1
Loading…
SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES
by
TOPACIO RODEN R
,
LOW YIP SENG
Year of Publication
04.07.2012
Get full text
Patent
Save to List
Saved in:
2
Loading…
CIRCUIT BOARD WITH VIA TRACE CONNECTION AND METHOD OF MAKING THE SAME
by
LEUNG ANDREW KW
,
MCLELLAN NEIL
,
LOW YIP SENG
Year of Publication
20.09.2012
Get full text
Patent
Save to List
Saved in:
3
Loading…
A METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
by
LEUNG ANDREW
,
MARTINEZ LIANE
,
TOPACIO RODEN
,
LOW YIP SENG
Year of Publication
17.04.2012
Get full text
Patent
Save to List
Saved in:
4
Loading…
SOLDER MASK WITH ANCHOR STRUCTURES
by
TOPACIO RODEN R
,
HSIEH YU LING
,
KW LEUNG ANDREW
,
LOW YIP SENG
Year of Publication
02.06.2014
Get full text
Patent
Save to List
Saved in:
5
Loading…
FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT
by
TOPACIO RODEN R
,
MARTINEZ LIANE
,
LOW YIP SENG
Year of Publication
01.09.2011
Get full text
Patent
Save to List
Saved in:
6
Loading…
Semiconductor chip with patterned underbump metallization and polymer film
by
Hu, Suming
,
Low
,
Yip Seng
,
Topacio, Roden R
Year of Publication
17.05.2022
Get full text
Patent
Save to List
Saved in:
7
Loading…
SOLDER MASK WITH ANCHOR STRUCTURES
by
TOPACIO, Roden, R
,
HSIEH, Yu-Ling
,
KW LEUNG, Andrew
,
LOW
,
Yip
,
Seng
Year of Publication
15.01.2020
Get full text
Patent
Save to List
Saved in:
8
Loading…
Circuit board with via trace connection and method of making the same
by
Low Yip Seng
,
McLellan Neil
,
Leung Andrew K W
Year of Publication
17.10.2017
Get full text
Patent
Save to List
Saved in:
9
Loading…
A METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS AND SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
by
MARTINEZ, Liane
,
LEUNG, Andrew
,
LOW
,
Yip Seng
,
TOPACIO, Roden
Year of Publication
11.10.2017
Get full text
Patent
Save to List
Saved in:
10
Loading…
"SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES"
by
LOW
,
YIP SENG
,
TOPACIO, RODEN, R
Year of Publication
31.07.2015
Get full text
Patent
Save to List
Saved in:
11
Loading…
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYMER FILM
by
Hu Suming
,
Low Yip Seng
,
Topacio Roden R
Year of Publication
20.04.2017
Get full text
Patent
Save to List
Saved in:
12
Loading…
Semiconductor chip with patterned underbump metallization and polymer film
by
Hu Suming
,
Low Yip Seng
,
Topacio Roden R
Year of Publication
21.02.2017
Get full text
Patent
Save to List
Saved in:
13
Loading…
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYMER FILM
by
TOPACIO RODEN R
,
HU SUMING
,
LOW YIP SENG
Year of Publication
01.10.2015
Get full text
Patent
Save to List
Saved in:
14
Loading…
SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES
by
LOW
,
YIP SENG
,
TOPACIO, RODEN R
Year of Publication
29.05.2013
Get full text
Patent
Save to List
Saved in:
15
Loading…
Face-to-face (F2F) hybrid structure for an integrated circuit
by
TOPACIO RODEN R
,
MARTINEZ LIANE
,
LOW YIP SENG
Year of Publication
27.05.2015
Get full text
Patent
Save to List
Saved in:
16
Loading…
A method of manufacturing substrates having asymmetric buildup layers
by
LEUNG ANDREW
,
MARTINEZ LIANE
,
TOPACIO RODEN
,
LOW YIP SENG
Year of Publication
15.04.2015
Get full text
Patent
Save to List
Saved in:
17
Loading…
A METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
by
LOW
,
YIP SENG
,
LEUNG, ANDREW
,
TOPACIO, RODEN
,
MARTINEZ, LIANE
Year of Publication
04.03.2015
Get full text
Patent
Save to List
Saved in:
18
Loading…
SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES
by
LOW
,
YIP SENG
,
TOPACIO, RODEN R
Year of Publication
18.07.2012
Get full text
Patent
Save to List
Saved in:
19
Loading…
Face-to-face (F2F) hybrid structure for an integrated circuit
by
TOPACIO RODEN R
,
MARTINEZ LIANE
,
LOW YIP SENG
Year of Publication
28.01.2014
Get full text
Patent
Save to List
Saved in:
20
Loading…
HEATSINK INTERPOSER
by
LOW
,
YIP SENG
,
TOPACIO, RODEN R
,
MARTINEZ, LIANE
Year of Publication
14.11.2013
Get full text
Patent
Save to List
Saved in:
1
2
3
4
Next
[4]
RSS Feed
Email Search
Save Search
Search History
Back
Refine Results
Page will reload when a filter is selected or excluded.
Limit to articles from scholarly journals
Limit to articles with full text available
Limit to Open Access content
Exclude newspaper articles
Include articles at other libraries
Expand results using synonyms
Format
Patent
61 results
61
Subject Area
chemistry
58 results
58
medicine
58 results
58
sciences
58 results
58
physics
2 results
2
Topic
electricity
58 results
58
basic electric elements
54 results
54
electric solid state devices not otherwise provided for
53 results
53
semiconductor devices
53 results
53
casings or constructional details of electric apparatus
18 results
18
electric techniques not otherwise provided for
18 results
18
See more
Language
English
61 results
61
French
19 results
19
German
10 results
10
Chinese
6 results
6
Korean
5 results
5
Year of Publication
From:
To:
Database
esp@cenet
58 results
58
USPTO Issued Patents
3 results
3
