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DRiLLS: Deep Reinforcement Learning for Logic Synthesis
Hosny, Abdelrahman, Hashemi, Soheil, Shalan, Mohamed, Reda, Sherief
Published in Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference (01.01.2020)
Published in Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference (01.01.2020)
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Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization
Liu, Meng-Yun, Lai, Yu-Cheng, Mak, Wai-Kei, Wang, Ting-Chi
Published in 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (29.10.2022)
Published in 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (29.10.2022)
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RTL Design and Logic Synthesis of Traffic Light Controller for 45nm Technology
Devipriya, A, Girish, H, Srinivas, Vishnu, Adi Reddy, Nitish, Rajkiran, D
Published in 2022 3rd International Conference for Emerging Technology (INCET) (27.05.2022)
Published in 2022 3rd International Conference for Emerging Technology (INCET) (27.05.2022)
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ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis
Pan, Hongyang, Zhu, Keren, Yang, Fan, Chu, Zhufei, Zeng, Xuan
Published in Proceedings - Design, Automation, and Test in Europe Conference and Exhibition (31.03.2025)
Published in Proceedings - Design, Automation, and Test in Europe Conference and Exhibition (31.03.2025)
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Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis
Pasandi, Ghasem, Peterson, Mackenzie, Herrera, Moises, Nazarian, Shahin, Massoud Pedram
Published in arXiv.org (03.07.2020)
Published in arXiv.org (03.07.2020)
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Lightweight Structural Choices Operator for Technology Mapping
Grosnit, Antoine, Zimmer, Matthieu, Tutunov, Rasul, Li, Xing, Chen, Lei, Yang, Fan, Yuan, Mingxuan, Bou-Ammar, Haitham
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
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DRiLLS: Deep Reinforcement Learning for Logic Synthesis
Abdelrahman Hosny, Hashemi, Soheil, Shalan, Mohamed, Reda, Sherief
Published in arXiv.org (13.11.2019)
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Published in arXiv.org (13.11.2019)
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Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis
Jiang, Jiaqing, Sun, Xiaoming, Teng, Shang-Hua, Wu, Bujiao, Wu, Kewen, Zhang, Jialin
Year of Publication 11.07.2019
Year of Publication 11.07.2019
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Optimal Space-Depth Trade-Off of CNOT Circuits in Quantum Logic Synthesis
Jiang, Jiaqing, Sun, Xiaoming, Shang-Hua Teng, Wu, Bujiao, Wu, Kewen, Zhang, Jialin
Published in arXiv.org (23.09.2022)
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Published in arXiv.org (23.09.2022)
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CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction
Chen-Hsuan Lin, Roy, Subhendu, Chun-Yao Wang, Pan, David Z., Deming Chen
Published in 2015 33rd IEEE International Conference on Computer Design (ICCD) (01.10.2015)
Published in 2015 33rd IEEE International Conference on Computer Design (ICCD) (01.10.2015)
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Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Roy, Subhendu, Choudhury, Mihir, Puri, Ruchir, Pan, David Z.
Published in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29.05.2013)
Published in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (29.05.2013)
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A computing origami: folding streams in FPGAs
Hagiescu, Andrei, Wong, Weng-Fai, Bacon, David F., Rabbah, Rodric
Published in 2009 46th ACM/IEEE Design Automation Conference (26.07.2009)
Published in 2009 46th ACM/IEEE Design Automation Conference (26.07.2009)
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Architecture of IoT-Based Collaborative Laboratory for Reconfigurable SoC: Review and Development
Al Amin, Rashed, Wiese, Veit, Rahman, Mohammad Musfiqur, Jacobs, Sven, Jaschke, Steffen, Obermaisser, Roman
Published in 2023 IEEE 2nd German Education Conference (GECon) (02.08.2023)
Published in 2023 IEEE 2nd German Education Conference (GECon) (02.08.2023)
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