26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB
Shang-Pin Chen, Chih-Chien Hung, Qui-Ting Chen, Sheng-Ming Chang, Ming-Shi Liou, Bo-Wei Hsieh, Hsiang-I Huang, Liu, Brian, Yan-Bin Luo
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Get full text
Conference Proceeding
Memory controller, memory module and memory system
Chen, Shang-Pin, Hsieh, Bo-Wei, Hung, Chih-Chien, Chang, Sheng-Ming, Liou, Ming-Shi, Luo, Yan-Bin
Year of Publication 25.09.2018
Get full text
Year of Publication 25.09.2018
Patent