A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
OH, Tae-Young, SOHN, Young-Soo, KIM, Jin-Hyun, KIM, Jin-Kook, KIM, Young-Sik, KIM, Byeong-Cheol, KWAK, Sang-Hyup, LEE, Jae-Hyung, LEE, Jae-Young, SHIN, Chang-Ho, YANG, Yunseok, CHO, Beom-Sig, BAE, Seung-Jun, BANG, Sam-Young, YANG, Hyang-Ja, CHOI, Young-Ryeol, MOON, Gil-Shin, PARK, Cheol-Goo, HWANG, Seok-Won, LIM, Jeong-Don, PARK, Kwang-Ii, JOO SUN CHOI, JUN, Young-Hyun, PARK, Min-Sang, LIM, Ji-Hoon, CHO, Yong-Ki, KIM, Dae-Hyun, KIM, Dong-Min, KIM, Hye-Ran, KIM, Hyun-Joong
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput
Lee, Seungjae, Kim, Chulbum, Kim, Minsu, Joe, Sung-min, Jang, Joonsuc, Kim, Seungbum, Lee, Kangbin, Kim, Jisu, Park, Jiyoon, Lee, Han-Jun, Kim, Minseok, Lee, Seonyong, Lee, SeonGeon, Bang, Jinbae, Shin, Dongjin, Jang, Hwajun, Lee, Deokwoo, Kim, Nahyun, Jo, Jonghoo, Park, Jonghoon, Park, Sohyun, Rho, Youngsik, Park, Yongha, Kim, Ho-joon, Lee, Cheon An, Yu, Chungho, Min, Youngsun, Kim, Moosung, Kim, Kyungmin, Moon, Seunghyun, Kim, Hyunjin, Choi, Youngdon, Ryu, YoungHwan, Choi, Jinwon, Lee, Minyeong, Kim, Jungkwan, Choo, Gyo Soo, Lim, Jeong-Don, Byeon, Dae-Seok, Song, Kiwhan, Park, Ki-Tae, Kyung, Kye-hyun
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
Published in 2018 IEEE International Solid - State Circuits Conference - (ISSCC) (01.02.2018)
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A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
Kim, Dae-Hyun, Song, Byungkyu, Ahn, Hyun-a, Ko, Woongjoon, Do, Sunggeun, Cho, Seokjin, Kim, Kihan, Oh, Seung-Hoon, Joo, Hye-Yoon, Park, Geuntae, Jang, Jin-Hun, Kim, Yong-Hun, Lee, Donghun, Jung, Jaehoon, Kwon, Yongmin, Kim, Youngjae, Jung, Jaewoo, O, Seongil, Lee, Seoulmin, Lim, Jaeseong, Son, Junho, Min, Jisu, Do, Haebin, Yoon, Jaejun, Hwang, Isak, Park, Jinsol, Shim, Hong, Yoon, Seryeong, Choi, Dongyeong, Lee, Jihoon, Woo, Soohan, Hong, Eunki, Choi, Junha, Kim, Jae-Sung, Han, Sangkeun, Bang, Jongmin, Park, Bokgue, Kim, Janghoo, Choi, Seouk-Kyu, Han, Gong-Heum, Sung, Yoo-Chang, Bae, Won-Il, Lim, Jeong-Don, Lee, Seungjae, Yoo, Changsik, Hwang, Sang Joon, Lee, Jooyoung
Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC) (20.02.2022)
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T- PLANAR T-COIL AND INTEGRATED CIRCUIT INCLUDING THE SAME
PARK JIN KWAN, YOO CHANG SIK, KIM JANG HOO, PARK YOON SUK, SUNG YOO CHANG, LIM JEONG DON
Year of Publication 26.01.2023
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Year of Publication 26.01.2023
Patent
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seung-Woo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Rajagopal, Devraj, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yong-Jin Kwon, Min-Jae Lee, Sung-Hoon Kim, Seung-Hoon Shin, Hyung-Gon Kim, Jin-Tae Kim, Ki-Sung Kim, Han-Sung Joo, Chan-Jin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kye-hyun Kyung, Jeong-Hyuk Choi
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
Published in 2015 IEEE International Solid State Circuits Conference (ISSCC) (01.02.2015)
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Journal Article
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
Published in 2010 IEEE International Solid-State Circuits Conference - (ISSCC) (01.02.2010)
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LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
LIM, JEONG DON, KIM, SI HONG, KIM, HYE RAN, SEOL, HO SEOK, BAE, SEUNG JUN
Year of Publication 20.08.2013
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Year of Publication 20.08.2013
Patent
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate
Kim, Doo-Hyun, Kim, Hyunggon, Yun, Sungwon, Song, Youngsun, Kim, Jisu, Joe, Sung-Min, Kang, Kyung-Hwa, Jang, Joonsuc, Yoon, Hyun-Jun, Lee, Kanabin, Kim, Minseok, Kwon, Joonsoo, Jo, Jonghoo, Park, Sehwan, Park, Jiyoon, Cho, Jisoo, Park, Sohyun, Kim, Garam, Bang, Jinbae, Kim, Heejin, Park, Jongeun, Lee, Deokwoo, Lee, Seonyong, Jang, Hwajun, Lee, Han-Jun, Shin, Donghyun, Park, Jungmin, Kim, Jungkwan, Kim, Jongmin, Jang, Kichang, Park, II Han, Moon, Seuna Hyun, Choi, Myung-Hoon, Kwak, Pansuk, Park, Joo-Yona, Choi, Youngdon, Kim, Sang-Lok, Lee, Seungjae, Kang, Dongku, Lim, Jeong-Don, Byeon, Dae-Seok, Song, Kiwhan, Choi, Junghwan, Hwang, Sang Joon, Jeong, Jaeheon
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
Published in 2020 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2020)
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