The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications
Venkatraman, R., Castagnetti, R., Kobozeva, O., Duan, F.L., Kamath, A., Sabbagh, S.T., Vilchis-Cruz, M.A., Liaw, J.J., Jyh-Cheng You, Ramesh, S.
Published in IEEE transactions on electron devices (01.02.2005)
Published in IEEE transactions on electron devices (01.02.2005)
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Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
Chang, Chih-Hao, Chang, V.S., Pan, K.H., Lai, K.T., Lu, J. H., Ng, J.A., Chen, C.Y., Wu, B.F., Lin, C.J., Liang, C.S., Tsao, C.P., Mor, Y.S., Li, C.T., Lin, T.C., Hsieh, C.H., Chen, P.N., Hsu, H.H., Chen, J.H., Chen, H.F., Yeh, J.Y., Chiang, M.C., Lin, C.Y., Liaw, J.J., Wang, C.H., Lee, S.B., Chen, C.C., Lin, H.J., Chen, R., Chen, K.W., Chui, C.O., Yeo, Y.C., Huang, K.B., Lee, T.L., Tsai, M.H., Chen, K.S., Lu, Y.C., Jang, S.M., Wu, S.-Y.
Published in 2022 International Electron Devices Meeting (IEDM) (01.01.2022)
Published in 2022 International Electron Devices Meeting (IEDM) (01.01.2022)
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Conference Proceeding
32nm gate-first high-k/metal-gate technology for high performance low power applications
Diaz, C.H., Goto, K., Huang, H.T., Yasuda, Yu, Tsao, C.P., Chu, T.T., Lu, W.T., Chang, V., Hou, Y.T., Chao, Y.S., Hsu, P.F., Chen, C.L., Lin, K.C., Ng, J.A., Yang, W.C., Chen, C.H., Peng, Y.H., Chen, C.J., Chen, C.C., Yu, M.H., Yeh, L.Y., You, K.S., Chen, K.S., Thei, K.B., Lee, C.H., Yang, S.H., Cheng, J.Y., Huang, K.T., Liaw, J.J., Ku, Y., Jang, S.M., Chuang, H., Liang, M.S.
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
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Conference Proceeding
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
Wu, Shien-Yang, Liaw, J.J., Lin, C.Y., Chiang, M.C., Yang, C.K., Cheng, J.Y., Tsai, M.H., Liu, M.Y., Wu, P.H., Chang, C.H., Hu, L.C., Lin, C.I., Chen, H.F., Chang, S.Y., Wang, S.H., Tong, P.Y., Hsieh, Y.L., Pan, K.H., Hsieh, C.H., Chen, C.H., Yao, C.H., Chen, C.C., Lee, T.L., Chang, C.W., Lin, H.J., Chen, S.C., Shieh, J.H., Tsai, M.H., Jang, S.M., Chen, K.S., Ku, Y., See, Y.C, Lo, W.J.
Published in 2009 Symposium on VLSI Technology (01.06.2009)
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Published in 2009 Symposium on VLSI Technology (01.06.2009)
Conference Proceeding
A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications
Wu, Shien-Yang, Chang, C.H., Chiang, M.C., Lin, C.Y., Liaw, J.J., Cheng, J.Y., Yeh, J.Y., Chen, H.F., Chang, S.Y., Lai, K.T., Liang, M.S., Pan, K.H., Chen, J.H., Chang, V.S., Luo, T.C., Wang, X., Mor, Y.S., Lin, C.I., Wang, S.H., Hsieh, M.Y., Chen, C.Y., Wu, B.F., Lin, C.J., Liang, C.S., Tsao, C.P., Li, C.T., Chen, C.H., Hsieh, C.H., Liu, H.H., Chen, P.N., Chen, C.C., Chen, R., Yeo, Y.C., Chui, C.O., Chang, W., Lee, T.L., Huang, K.B., Lin, H.J., Chen, K.W., Tsai, M.H., Chen, K.S., Chen, X.M., Cheng, Y.K., Wang, C.H., Shue, W., Ku, Y., Jang, S. M., Cao, M., Lu, L.C., Chang, T.S.
Published in 2022 International Electron Devices Meeting (IEDM) (03.12.2022)
Published in 2022 International Electron Devices Meeting (IEDM) (03.12.2022)
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Conference Proceeding
TEXTURE CHARACTERISTICS OF ALLERGENIC POLLENS
JUANG, L.C., LUO, C.H., LIAW, J.J., LIN, M.I., LEE, Y.S.
Published in Journal of aerosol science (01.07.2004)
Published in Journal of aerosol science (01.07.2004)
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Journal Article
Absence of androgen-mediated transcriptional effects in osteoblastic cells despite presence of androgen receptors
Czerwiec, F.S., Liaw, J.J., Liu, S.-B., Perez-Stable, C., Grumbles, R., Howard, G.A., Roos, B.A., Burnstein, K.L.
Published in Bone (New York, N.Y.) (01.07.1997)
Published in Bone (New York, N.Y.) (01.07.1997)
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Journal Article
Optimization of 2.14 um/sup 2/ 6T-SRAM cell by using cell-like test structures
Hsieh, S., Tsui, R.F., Lin, W., Liaw, J.J., Doong, K.Y., Wu, C.-M.M.
Published in Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516) (2004)
Published in Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516) (2004)
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Conference Proceeding
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
Shien-Yang Wu, Chou, C.W., Lin, C.Y., Chiang, M.C., Yang, C.K., Liu, M.Y., Hu, L.C., Chang, C.H., Wu, P.H., Chen, H.F., Chang, S.Y., Wang, S.H., Tong, P.Y., Hsieh, Y.L., Liaw, J.J., Pan, K.H., Hsieh, C.H., Chen, C.H., Cheng, J.Y., Yao, C.H., Wan, W.K., Lee, T.L., Huang, K.T., Lin, K.C., Yeh, L.Y., Ku, K.C., Chen, S.C., Lin, H.J., Jang, S.M., Lu, Y.C., Shieh, J.H., Tsai, M.H., Song, J.Y., Chen, K.S., Chang, V., Cheng, S.M., Yang, S.H., Diaz, C.H., See, Y.C., Liang, M.S.
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
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Conference Proceeding
Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications
Wu, C.C., Diaz, C.H., Lin, B.L., Chang, S.Z., Wang, C.C., Liaw, J.J., Wang, C.H., Young, K.K., Lee, K.H., Liew, B.K., Sun, J.Y.C.
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
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Conference Proceeding
Extended 0.13 /spl mu/m CMOS technology for the ultra high-speed and MS/RF application segments
Chang, C.S., Chao, C.P., Leung, Y.K., Lin, C.H., Hsu, H.-M., Wang, Y.P., Chang, S.Y., Chiu, T.H., Shyu, J.S., Wu, C.C., Wang, C.H., Chang, R.Y., Chen, C.W., Huang, C.F., Chen, C.H., Chen, S.H., Yeh, T.H., Cheng, J.Y., Liaw, J.J., Chu, Y.L., Ong, T.C., Yu, M.C., Yu, C.H., Lin, H.J., Tao, H.J., Liang, M.S., See, Y.C., Diaz, C.H., Sun, Y.C.
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
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Conference Proceeding
A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications
Diaz, C.H., Young, K.L., Hsu, J.H., Lin, J.C.H., Hou, C.S., Lin, C.T., Liaw, J.J., Wu, C.C., Su, C.W., Wang, C.H., Ting, J.K., Yang, S.S., Lee, K.Y., Wu, S.Y., Tsai, C.C., Tao, H.J., Jang, S.M., Shue, S.L., Hsieh, H.C., Wang, Y.Y., Chen, C.C., Yang, S.C., Fu, S., Chang, S.Z., Lo, T.C., Wu, J.Y., Shy, J.S., Liu, C.W., Chen, S.H., Lin, B.L., Liew, B.K., Yen, T., Yu, C.H., Chao, Y.C., Liang, M.S., Wang, C., Sun, J.Y.C.
Published in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) (1999)
Published in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) (1999)
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