First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
Cheng, Chao-Ching, Chung, Yun-Yan, Li, Uing-Yang, Lin, Chao-Ting, Li, Chi-Feng, Chen, Jyun-Hong, Lai, Tung-Yen, Li, Kai-Shin, Shieh, Jia-Min, Su, Sheng-Kai, Chiang, Hung-Li, Chen, Tzu-Chiang, Li, Lain-Jong, Wong, H.-S. Philip, Chien, Chao-Hsin
Published in 2019 Symposium on VLSI Technology (01.06.2019)
Published in 2019 Symposium on VLSI Technology (01.06.2019)
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