Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2^) Using Symmetric TMVP and Block Recombination Techniques
Chiou-Yng Lee, Meher, Pramod Kumar
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2015)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.12.2015)
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Journal Article
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures
Bayat-Sarmadi, Siavash, Kermani, Mehran Mozaffari, Azarderakhsh, Reza, Chiou-Yng Lee
Published in IEEE transactions on circuits and systems. II, Express briefs (01.02.2014)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.02.2014)
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Journal Article
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition
Chiou-Yng Lee, Meher, Pramod Kumar
Published in IEEE transactions on circuits and systems. I, Regular papers (01.03.2015)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.03.2015)
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Journal Article
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications
Azarderakhsh, Reza, Kermani, Mehran Mozaffari, Bayat-Sarmadi, Siavash, Chiou-Yng Lee
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2015)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2015)
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Journal Article
Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2/sup m/)
Lee, Chiou-Yng, Horng, Jenn-Shyong, Jou, I-Chang, Lu, Erl-Huei
Published in IEEE transactions on computers (01.09.2005)
Published in IEEE transactions on computers (01.09.2005)
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Journal Article
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b,2)-Way Karatsuba Decomposition
Chiou-Yng Lee, Chun-Sheng Yang, Meher, Bimal Kumar, Meher, Pramod Kumar, Jeng-Shyang Pan
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2014)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2014)
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Journal Article
Reduction of space complexity based on symmetric TMVP
Yang, Chunsheng, Pan, Jeng-Shyang, Lee, Chiou-Yng, Yan, Lijun
Published in Electronics letters (30.04.2015)
Published in Electronics letters (30.04.2015)
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Journal Article
Low-Complexity Digit-Serial Multiplier Over GF(2^) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
Chiou-Yng Lee, Meher, Pramod Kumar, Chia-Chen Fan, Shyan-Ming Yuan
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2017)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2017)
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Journal Article
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
Pan, Jeng-Shyang, Lee, Chiou-Yng, Sghaier, Anissa, Zeghid, Medien, Xie, Jiafeng
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2019)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.07.2019)
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Journal Article