Search Results - "Ledalla, Ravi" :: K.UTB vyhledávací portál

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

by Ledalla, Ravi, Sinha, Debjit, Bhanji, Adil, Li, Chaobo, Schaeffer, Gregory, Gupta, Hemlata, Basile, Jennifer
Published in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.02.2021)

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Conference Proceeding

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Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

by Sinha, Debjit, Schaeffer, Gregory, Li, Chaobo, Wood, Michael Hemsley, Bhanji, Adil, Ledalla, Ravi Chander
Year of Publication 10.11.2020

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Patent

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

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