Device specific characterization of yield limiting pattern geometries by combining layout profiling with high sensitivity wafer inspection
Le Denmat, Jean-Christophe, Tetar, Laurent, Fanton, Pierre, Yesilada, Emek, Goirand, Pierre-Jerome, Narasimhan, Narayani, Parisi, Paolo, Ramachandran, Vijay, Kekare, Sagar A.
Published in 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) (01.05.2015)
Published in 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) (01.05.2015)
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