A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs
Renaud, Guillaume, Barragan, Manuel J., Laraba, Asma, Stratigopoulos, Haralampos-G., Mir, Salvador, Le-Gall, Hervé, Naudet, Hervé
Published in Journal of electronic testing (01.08.2016)
Published in Journal of electronic testing (01.08.2016)
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Journal Article
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel Zhaoyin, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan
Published in IEEE journal of solid-state circuits (01.04.2022)
Published in IEEE journal of solid-state circuits (01.04.2022)
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Journal Article
A 112-134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET
de Abreu Farias Neto, Pedro Wilson, Hearne, Kay, Chlis, Ilias, Carey, Declan, Casey, Ronan, Griffin, Ben, Ngankem Ngankem, Frantz Stephane F., Hudner, James, Geary, Kevin, Erett, Marc, Laraba, Asma, Eachempatti, Haritha, Kim, Jae Wook, Zhang, Hongtao, Asuncion, Santiago, Frans, Yohan
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
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Journal Article
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC
Vaz, Bruno, Lynam, Adrian, Verbruggen, Bob, Laraba, Asma, Mesadri, Conrado, Boumaalif, Ali, Mcgrath, John, Kamath, Umanath, De Le Torre, Ronnie, Manlapat, Alvin, Breathnach, Daire, Erdmann, Christophe, Farley, Brendan
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
Reduced code linearity testing of pipeline adcs in the presence of noise
Laraba, A., Stratigopoulos, H., Mir, S., Naudet, H., Bret, G.
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.01.2013)
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.01.2013)
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Conference Proceeding
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET
Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
Published in 2021 Symposium on VLSI Circuits (13.06.2021)
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Conference Proceeding
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET
Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Circuits (01.06.2018)
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Conference Proceeding
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs
Laraba, A., Stratigopoulos, H-G, Mir, S., Naudet, H., Forel, C.
Published in 2012 17th IEEE European Test Symposium (ETS) (01.05.2012)
Published in 2012 17th IEEE European Test Symposium (ETS) (01.05.2012)
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Conference Proceeding