Search Results - "Lan-Chou Cho" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

by Feng-Wei Kuo, Binsfeld Ferreira, Sandro, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Madadi, Iman, Tohidian, Massoud, Shahmohammadi, Mina, Babaie, Masoud, Bogdan Staszewski, Robert
Published in IEEE journal of solid-state circuits (01.04.2017)

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Journal Article

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

by Babaie, Masoud, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Shahmohammadi, Mina, Staszewski, Robert Bogdan
Published in IEEE journal of solid-state circuits (01.07.2016)

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Journal Article

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

by Kuo, Feng-Wei, Babaie, Masoud, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2018)

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Journal Article

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

by Xu, Kai, Kuo, Feng-Wei, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan
Published in IEEE journal of solid-state circuits (01.07.2019)

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Journal Article

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

by Chi-Yao Yu, Lu, I. S., Yen-Horng Chen, Lan-Chou Cho, Sun, C. E., Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, Chien, G.
Published in IEEE journal of solid-state circuits (01.12.2011)

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Journal Article Conference Proceeding

A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology

A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology

by CHO, Lan-Chou, LEE, Chihun, LIU, Shen-Iuan
Published in IEEE journal of solid-state circuits (01.06.2007)

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Journal Article

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

by CHO, Lan-Chou, LEE, Chihun, HUNG, Chao-Ching, LIU, Shen-Iuan
Published in IEEE journal of solid-state circuits (01.03.2009)

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Journal Article

$A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS$

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-$\mu$m CMOS

by Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
Published in IEEE transactions on circuits and systems. II, Express briefs (01.05.2008)

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Journal Article

A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna

A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna

by Jing-Hong Conan Zhan, Yuli Hsueh, Min Chen, Meng-Hsiung Hung, Yi-An Li, Lan-Chou Cho, Hui-Hsien Liu, Ming-Da Tsai, Ping-Yu Chen, Jui-Lin Syu, Yi-Chien Tsai, Tao-Yao Chang, Jen-Che Tsai, Sheng-Hao Chen, Ping-Hsuan Tsu, Kuo-Hao Chen, Chun-Yi Wu, Sheng Jau Wong, Chun Geik Tan, Chien, George
Published in 2014 IEEE Radio Frequency Integrated Circuits Symposium (01.06.2014)

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Conference Proceeding

Cascaded Multi-Stage Directional Coupler on Silicon-on-Insulator

Cascaded Multi-Stage Directional Coupler on Silicon-on-Insulator

by Tang, Cheng-Tse, Jou, Chewn-Pu, Cho, Lan-Chou, Kuo, Fong-Wei, Chung, Ming-Yang, Huang, Tai-Chun, Hung, Yung-Jr
Published in 2022 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR) (31.07.2022)

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Conference Proceeding

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

by Kuo, Feng-Wei, Zong, Zhirui, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan
Published in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) (01.09.2019)

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Conference Proceeding

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

by Chihun Lee, Lan-Chou Cho, Shen-Iuan Liu
Published in IEEE Custom Integrated Circuits Conference 2006 (01.09.2006)

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Conference Proceeding

Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

by Kuo, Feng-Wei, Ferreira, Sandro Binsfeld, Chen, Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Babaie, Masoud, Staszewski, Robert Bogdan
Published in 2018 IEEE/MTT-S International Microwave Symposium - IMS (01.06.2018)

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Conference Proceeding

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

by Lu, I S.-C, Chi-yao Yu, Yen-horng Chen, Lan-chou Cho, Sun, Chih-hao Eric, Chih-Chun Tang, Chien, G
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)

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Conference Proceeding

$A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mum CMOS$

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- \mum CMOS

by Lee, Chihun, Cho, Lan-Chou, Wu, Jia-Hao, Liu, Shen-Iuan
Published in IEEE transactions on circuits and systems. II, Express briefs (01.05.2008)

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Journal Article

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

by Cho, Lan-Chou, Lee, Chihun, Liu, Shen-Iuan
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)

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Conference Proceeding

$A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS$

A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

by Feng-Wei Kuo, Pourmousavian, Seyednaser, Siriburanon, Teerachot, Ron Chen, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Staszewski, Robert Bogdan
Published in 2017 Symposium on VLSI Circuits (01.06.2017)

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Conference Proceeding

A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation

A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation

by Xu, Kai, Kuo, Feng-Wei, Chen, Huan-Neng Ron, Cho, Lan-Chou, Jou, Chewn-Pu, Chen, Mark, Staszewski, Robert Bogdan
Published in IEEE journal of solid-state circuits (01.07.2019)

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Journal Article

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

by Feng-Wei Kuo, Binsfeld Ferreira, Sandro, Babaie, Masoud, Chen, Ron, Lan-chou Cho, Chewn-Pu Jou, Fu-Lung Hsueh, Guanzhong Huang, Madadi, Iman, Tohidian, Massoud, Staszewski, Robert Bogdan
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)

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Conference Proceeding

A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

by Lan-Chou Cho, Feng-Wei Kuo, Ron Chen, Liu, Jack, Chewn-Pu Jou, Fu-Lung Hsueh, Staszewski, R. Bogdan
Published in 2017 Symposium on VLSI Circuits (01.06.2017)

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Conference Proceeding

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