64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
Heald, R., Shin, K., Reddy, V., I-Feng Kao, Khan, M., Lynch, W.L., Lauterbach, G., Petolino, J.
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
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Journal Article
Low load latency through sum-addressed memory (SAM)
Lynch, William L., Lauterbach, Gary, Chamdani, Joseph I.
Published in Proceedings of the 25th annual international symposium on Computer architecture (16.04.1998)
Published in Proceedings of the 25th annual international symposium on Computer architecture (16.04.1998)
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Conference Proceeding
Packet routing and switching device
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Year of Publication 28.07.2015
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Year of Publication 28.07.2015
Patent
PACKET ROUTING AND SWITCHING DEVICE
LYNCH WILLIAM L, BARNES PETER M, LI ANTHONY J, MEHROTRA SHARED, JAYARAM NIKHIL
Year of Publication 20.12.2012
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Year of Publication 20.12.2012
Patent
Packet routing and switching device
Barnes, Peter M, Jayaram, Nikhil, Li, Anthony J, Lynch, William L, Mehrotra, Sharad
Year of Publication 18.09.2012
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Year of Publication 18.09.2012
Patent