(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)
Triyoso, Dina, Carter, Rick, Kluth, Jon, Luning, Scott, Child, Amy, Wahl, Jeremy, Mulfinger, Bob, Punchihewa, Kasun, Kumar, Anil, Kang, Laegu, Sporer, Ryan, Chen, Xiaobo, Straub, Sherry, Bohra, Girish, Patil, Suraj, Zhang, Xing, Chen, Alex, Togo, Mitsuhiro, Pal, Rohit
Published in ECS transactions (08.09.2015)
Published in ECS transactions (08.09.2015)
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Journal Article
Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology
Liu, Qing, Yagishita, Atsushi, Kumar, Arvind, Loubet, Nicolas, Yamamoto, Toyoji, Kulkarni, Pranita, Monsieur, Frederic, Khakifirooz, Ali, Ponoth, Shom, Cheng, Kangguo, Haran, Bala, Vinet, Maud, Cai, Jin, Khare, Prasanna, Monfray, Stephane, Boeuf, Frederic, Mehta, Sanjay, Kuss, James, Leobandung, Effendi, Hane, Masami, Bu, Huiming, Ishimaru, Kazunari, Skotnicki, Thomas, Kleemeier, Walter, Takayanagi, Mariko, Hook, Terence, Khare, Mukesh, Luning, Scott, Doris, Bruce, Sampson, Ron
Published in ECS transactions (01.01.2011)
Published in ECS transactions (01.01.2011)
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Journal Article
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
Doris, Bruce B, Loubet, Nicolas, Cheng, Kangguo, Luning, Scott, Liu, Qing, Khakifirooz, Ali
Year of Publication 16.04.2019
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Year of Publication 16.04.2019
Patent
Simplified gate to source/drain region connections
Punchihewa, Kasun Anupama, Neogi, Tuhin Guha, Luning, Scott D, Pritchard, David
Year of Publication 15.01.2019
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Year of Publication 15.01.2019
Patent
SIMPLIFIED GATE TO SOURCE/DRAIN REGION CONNECTIONS
Punchihewa, Kasun Anupama, Neogi, Tuhin Guha, Luning, Scott D, Pritchard, David
Year of Publication 23.08.2018
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Year of Publication 23.08.2018
Patent