SOC Test Architecture and Method for 3-D ICs
Lo, Chih-Yen, Hsing, Yu-Tsao, Denq, Li-Ming, Wu, Cheng-Wen
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2010)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.10.2010)
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Journal Article
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
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Conference Proceeding
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs
Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
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Conference Proceeding
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
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Conference Proceeding
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs
Yun-Chao Yu, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
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Conference Proceeding
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs
Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
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Conference Proceeding
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
Yun-Chao Yu, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
Published in 2013 IEEE 31st VLSI Test Symposium (VTS) (01.04.2013)
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Conference Proceeding
A built-in self-test scheme for 3D RAMs
Yun-Chao Yu, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2012 IEEE International Test Conference (01.11.2012)
Published in 2012 IEEE International Test Conference (01.11.2012)
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Conference Proceeding
Test Integration for SOC Supporting Very Low-Cost Testers
Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
Published in 2009 Asian Test Symposium (01.11.2009)
Published in 2009 Asian Test Symposium (01.11.2009)
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Conference Proceeding
An FPGA-based test platform for analyzing data retention time distribution of DRAMs
Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
Published in 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) (01.04.2013)
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Conference Proceeding
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method
Hsieh, Tsung-Fu, Li, Jin-Fu, Lai, Jenn-Shiang, Lo, Chih-Yen, Kwai, Ding-Ming, Chou, Yung-Fa
Published in 2020 IEEE International Test Conference in Asia (ITC-Asia) (01.09.2020)
Published in 2020 IEEE International Test Conference in Asia (ITC-Asia) (01.09.2020)
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Conference Proceeding
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction
Hu, Jia-Yun, Hou, Kuan-Wei, Lo, Chih-Yen, Chou, Yung-Fa, Wu, Cheng-Wen
Published in 2018 IEEE International Test Conference in Asia (ITC-Asia) (01.08.2018)
Published in 2018 IEEE International Test Conference in Asia (ITC-Asia) (01.08.2018)
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Conference Proceeding
An SOC test integration platform and its industrial realization
CHENG, Kuo-Liang, HUANG, Jing-Reng, WANG, Chih-Wea, LO, Chih-Yen, DENQ, Li-Ming, HUANG, Chih-Tsun, WU, Cheng-Wen, HUNG, Shin-Wei, LEE, Jye-Yuan
Published in 2004 International Conferce on Test (2004)
Published in 2004 International Conferce on Test (2004)
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Conference Proceeding
A network security processor design based on an integrated SOC design and test platform
Wang, Chen-Hsing, Lo, Chih-Yen, Lee, Min-Sheng, Yeh, Jen-Chieh, Huang, Chih-Tsun, Wu, Cheng-Wen, Huang, Shi-Yu
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006 (24.07.2006)
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006 (24.07.2006)
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Conference Proceeding
A channel-sharable built-in self-test scheme for multi-channel DRAMs
Wu, Kuan-Te, Li, Jin-Fu, Lo, Chih-Yen, Lai, Jenn-Shiang, Kwai, Ding-Ming, Chou, Yung-Fa
Published in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2018)
Published in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2018)
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Conference Proceeding
A hybrid built-in self-test scheme for DRAMs
Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
Published in VLSI Design, Automation and Test(VLSI-DAT) (01.04.2015)
Published in VLSI Design, Automation and Test(VLSI-DAT) (01.04.2015)
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Conference Proceeding
Hierarchical Test Integration Methodology for 3-D ICs
Chou, Che-Wei, Li, Jin-Fu, Yu, Yun-Chao, Lo, Chih-Yen, Kwai, Ding-Ming, Chou, Yung-Fa
Published in IEEE design and test (01.08.2015)
Published in IEEE design and test (01.08.2015)
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Magazine Article