Thermal effect of 0.1 μm partially depleted SOI CMOSFET
Yeh, W.K, Huang, C, Chen, T.F, Hsu, S, Liu, J, Liou, F.T
Published in Microelectronic engineering (01.11.2001)
Published in Microelectronic engineering (01.11.2001)
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Identification of Si/SiO2 interface properties in thin film transistors with charge pumping technique
BALASINSKI, A, WORLEY, J, HUANG, K. W, LIOU, F. T
Published in Journal of the Electrochemical Society (01.08.1995)
Published in Journal of the Electrochemical Society (01.08.1995)
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Mechanism of Threshold Voltage Shift (Δ V th ) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs
Liu, Chuan-Hsi, Lee, Ming T., Lin, Chih-Yung, Chen, Jenkon, Loh, Y. T., Liou, Fu-Tai, Schruefer, Klaus, Katsetos, Anastasios A., Yang, Zhijian, Rovedo, Nivo, Hook, Terence B., Wann, Clement, Chen, Tze-Chiang
Published in Japanese Journal of Applied Physics (2002)
Published in Japanese Journal of Applied Physics (2002)
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Observation of two types of trapping centers in thin film transistors using charge pumping technique
Balasinski, A., Worley, J., Huang, K.W., Walters, J., Liou, F.T.
Published in IEEE electron device letters (01.10.1995)
Published in IEEE electron device letters (01.10.1995)
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Solid electrochemical modification of semiconductors
Yang, C.Y., Liou, F-T., Levine, S.N., Srinivasan, S.
Published in Solid state communications (01.01.1982)
Published in Solid state communications (01.01.1982)
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Polycrystalline In2O3 and In2O3/Y2O3 photoanodes
Liou, F. -T., Yang, C. Y., Hakim, K., Levine, S. N.
Published in Journal of applied electrochemistry (01.05.1983)
Published in Journal of applied electrochemistry (01.05.1983)
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Thin dielectric quality/yield study using a constant voltage ramp method
BRYANT, F, LIOU, F.-T, HAN, Y.-P, BARNES, J. J
Published in Journal of the Electrochemical Society (1989)
Published in Journal of the Electrochemical Society (1989)
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A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array
Liou, F.-T., Han, Y.-P., Bryant, F.R., Zamanian, M.
Published in IEEE journal of solid-state circuits (01.04.1989)
Published in IEEE journal of solid-state circuits (01.04.1989)
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A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12∼16A) gate oxide
CHUNG, Steve S, CHEN, S.-J, CHIEN, S.-C, LIOU, F.-T, WEN, Frank, YANG, C.-K, CHENG, S.-M, LIN, S.-H, SHENG, Y.-C, LIN, H.-S, HUNG, K.-T, WU, D.-Y, YEW, T.-R
Year of Publication 2002
Year of Publication 2002
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A 0.8-mu m CMOS technology for high-performance ASIC memory andchannelless gate array
Liou, F-T, Han, Y-P, Bryant, F R, Zamanian, M
Published in IEEE journal of solid-state circuits (01.04.1989)
Published in IEEE journal of solid-state circuits (01.04.1989)
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Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology
Liou, F.T., Chen, F.S., Dixit, G.A., Zamanian, M., DeSanti, G.
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
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Polycrystalline In sub(2)O sub(3) and In sub(2)O sub(3)/Y sub(2)O sub(3) photoanodes
Liou, F-T, Yang, C Y, Hakim, K, Levine, S N
Published in Journal of applied electrochemistry (01.01.1983)
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Published in Journal of applied electrochemistry (01.01.1983)
Journal Article
A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide
Chung, S.S., Chen, S.-J., Yang, C.-K., Cheng, S.-M., Lin, S.-H., Sheng, Y.-C., Lin, H.-S., Hung, K.-T., Wu, D.-Y., Yew, T.-R., Chien, S.-C., Liou, F.-T., Wen, F.
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
Published in 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) (2002)
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A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process
Sundaresan, R., Wei, C.C., Zamanian, M., Chen, F.S., Miller, R.O., Hodges, R.L., Gaskins, W., Sagarwala, P., Nguyen, L., Huang, J., Spinner, C., Stagaman, G.S., Lu, L., Lin, Y.S., Bryant, F., Liou, F.T.
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
Published in 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers (1991)
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Extending the reliability scaling limit of gate dielectrics through remote plasma nitridation of N2O-Grown oxides and NO RTA treatment
LIU, Chuan H, LIN, Hsiu-Shan, LEE, J. H, HUANG, M, HSIUNG, Chiung-Sheng, HUANG-LU, S, HSU, Chen-Chung, LIANG, Alan Y, JENKON CHEN, HSIEH, W. Y, YEN, P. W, CHIEN, S. C, LIN, Yu-Yin, LOH, Y. T, CHANG, Yih J, LIOU, Fu-Tai, CHEN, M. G, PAN, T. M, KAO, C. J, HUANG, K. T, LIN, S. H, SHENG, Y. C, CHANGE, Wen-Tung
Year of Publication 2002
Year of Publication 2002
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Planarized aluminum metallization for sub-0.5 mu m CMOS technology
Chen, F.S., Lin, Y.S., Dixit, G.A., Sundaresan, R., Wei, C.C., Liou, F.T.
Published in International Technical Digest on Electron Devices (1990)
Published in International Technical Digest on Electron Devices (1990)
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Reliability study of planarized aluminum metallization
Hoang, H.H., Chen, F.S., Zamanian, M., Dixit, G.A., Wei, C.C., Liou, F.T.
Published in 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference (1991)
Published in 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference (1991)
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