A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok
Published in IEEE journal of solid-state circuits (01.04.2014)
Published in IEEE journal of solid-state circuits (01.04.2014)
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Journal Article
Interconnect in the Era of 3DIC
Li, Shenggao, Lin, Mu-Shan, Chen, Wei-Chih, Tsai, Chien-Chun
Published in 2022 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2022)
Published in 2022 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2022)
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Conference Proceeding
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
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Conference Proceeding
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing
Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Cheng-Hsiang, Chen, Tom, Huang, Wen-Hung, Hu, Jack, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok
Published in 2013 Symposium on VLSI Technology (01.06.2013)
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Published in 2013 Symposium on VLSI Technology (01.06.2013)
Conference Proceeding
A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Tsung-Hsin Yu, Jinn-Yeh Chien, Chen, W.D., Chi-Chang Lu, Wei-Chih Chen, Fu, J., Yang, S.J., Chien-Hung Chen, Kuo-Liang Deng, Wen, C.H., Wang, L.Y.
Published in 2009 IEEE Asian Solid-State Circuits Conference (01.11.2009)
Published in 2009 IEEE Asian Solid-State Circuits Conference (01.11.2009)
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Conference Proceeding
A 7-nm 4-GHz Arm^1-Core-Based CoWoS^1 Chiplet Design for High-Performance Computing
Lin, Mu-Shan, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi
Published in IEEE journal of solid-state circuits (26.02.2020)
Published in IEEE journal of solid-state circuits (26.02.2020)
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Journal Article
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package
Mu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Chen, Y.-H, Kuo, C.-C, Shih-Peng Tai, Yamada, Kazuyoshi
Published in 2016 IEEE Hot Chips 28 Symposium (HCS) (01.08.2016)
Published in 2016 IEEE Hot Chips 28 Symposium (HCS) (01.08.2016)
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Conference Proceeding
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
Lin, Mu-Shan, Tsai, Chien-Chun, Li, Shenggao, Huang, Tze-Chiang, Huang, Wen-Hung, Huang, Kate, Chen, Yu-Chi, Liu, Alex, Huang, Yu-Jie, Wang, Jimmy, Yang, Shu-Chun, Cheng, Nai-Chen, Li, Chao-Chieh, Kuo, Hsin-Hung, Chen, Wei-Chih, Wen, C.H., Lin, Kevin, Huang, Po-Yi, Hsieh, Kenny Cheng-Hsiang, Lee, Frank
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
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Conference Proceeding