Search Results - "LIAO SZUYA S" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME

by BOHR MARK, LIAO SZUYA S, WEBB MILTON CLAIR, GHANI TAHIR
Year of Publication 14.07.2020

Get full text

Patent

DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CONTACTS

DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CONTACTS

by LIAO SZUYA S, KOBRINSKY MAURO J, KUMAR RAJESH, TAN ELLIOT, SIVAKUMAR SWAMINATHAN, GHANI TAHIR, GOMES WILFRED
Year of Publication 01.07.2021

Get full text

Patent

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

by LIAO SZUYA S, HOURANI RAMI, CLENDENNING SCOTT B, KLOSTER GRANT M, MITAN MARTIN M, GSTREIN FLORIAN, ROMERO PATRICIO E
Year of Publication 02.06.2021

Get full text

Patent

자기 정렬 게이트 에지 트라이게이트 및 FINFET 디바이스들

자기 정렬 게이트 에지 트라이게이트 및 FINFET 디바이스들

by LIAO SZUYA S, GUHA BISWAJEET, KENYON CHRISTOPHER N, GULER LEONARD P, GHANI TAHIR
Year of Publication 13.02.2019

Get full text

Patent

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

by LIAO SZUYA S, HATTENDORF MICHAEL L, GHANI TAHIR
Year of Publication 02.12.2016

Get full text

Patent

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME

by BOHR MARK, LIAO SZUYA S, WEBB MILTON CLAIR, GHANI TAHIR
Year of Publication 18.08.2016

Get full text

Patent

SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES

SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES

by HOURANI RAMI, LIAO SZUYA S, CLENDENNING SCOTT B, KLOSTER GRANT, ROMERO PATRICIO E, GSTREIN FLORIAN
Year of Publication 23.08.2017

Get full text

Patent

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

by LIAO SZUYA S, HOURANI RAMI, CLENDENNING SCOTT B, KLOSTER GRANT M, MITAN MARTIN M, GSTREIN FLORIAN, ROMERO PATRICIO E
Year of Publication 08.06.2017

Get full text

Patent

SEMICONDUCTOR DEVICE CONTACTS WITH INCREASED CONTACT AREA

SEMICONDUCTOR DEVICE CONTACTS WITH INCREASED CONTACT AREA

by MEHANDRU, Rishabh, LIAO, Szuya S, GHANI, Tahir
Year of Publication 05.06.2024

Get full text

Patent

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

by Liao, Szuya S, Patel, Pratik A
Year of Publication 20.02.2024

Get full text

Patent

Confined epitaxial regions for semiconductor devices

Confined epitaxial regions for semiconductor devices

by Ghani, Tahir, Liao, Szuya S, Hattendorf, Michael L
Year of Publication 17.09.2024

Get full text

Patent

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

by Liao, Szuya S, Jain, Anurag, Baykan, Mehmet O
Year of Publication 30.01.2024

Get full text

Patent

FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K DIELECTRIC MATERIAL

FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K DIELECTRIC MATERIAL

by Liao, Szuya S, Patel, Pratik A
Year of Publication 10.03.2022

Get full text

Patent

MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES

MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES

by BAYKAN, Mehmet O, LIAO, Szuya S, JAIN, Anurag
Year of Publication 26.10.2023

Get full text

Patent

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

by Liao, Szuya S, Patel, Pratik A
Year of Publication 23.11.2021

Get full text

Patent

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS

by LIAO, Szuya S, HATTENDORF, Michael L, GHANI, Tahir
Year of Publication 06.07.2023

Get full text

Patent

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT

by Bohr, Mark, Ghani, Tahir, Liao, Szuya S, Webb, Milton Clair
Year of Publication 08.06.2023

Get full text

Patent

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

by Ghani, Tahir, Liao, Szuya S, Hattendorf, Michael L
Year of Publication 02.05.2023

Get full text

Patent

Self-aligned gate edge and local interconnect

Self-aligned gate edge and local interconnect

by Bohr, Mark, Ghani, Tahir, Liao, Szuya S, Webb, Milton Clair
Year of Publication 24.01.2023

Get full text

Patent

Source or drain structures with high germanium concentration capping layer

Source or drain structures with high germanium concentration capping layer

by Patel, Pratik, Liao, Szuya S, Tolstova, Yulia, Vishwanath, Suresh, Bomberger, Cory, Murthy, Anand S
Year of Publication 02.07.2024

Get full text

Patent

1
2
3
4
5
6
7
8
9
10
11
Next
[12]