DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
LEGER; GEARY, WISHNEUSKY; JOHN ANDREW, BENJARAM; BHOOPAL R, CARPENTER; PETER R, SCHAPS; GARY L
Year of Publication 14.07.1998
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Year of Publication 14.07.1998
Patent
DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer
LEGER; GEARY L, WISHNEUSKY; JOHN ANDREW, BENJARAM; BHOOPAL R, CARPENTER; PETER R, SCHAPS; GARY L
Year of Publication 09.06.1998
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Year of Publication 09.06.1998
Patent
Switched memory module
HERRUD; JAMES E, LEGER; GEARY L, MAURITZ; KARL H, WICKLUND; JOSEPH B, LANEY; STEVEN H
Year of Publication 21.11.1989
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Year of Publication 21.11.1989
Patent