A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology
LEE, Hyun-Woo, KIM, Ki-Han, CHOI, Young-Kyoung, SOHN, Ju-Hwan, PARK, Nak-Kyu, KIM, Kwan-Weon, KIM, Chulwoo, CHOI, Young-Jung, CHUNG, Byong-Tae
Published in IEEE journal of solid-state circuits (01.01.2012)
Published in IEEE journal of solid-state circuits (01.01.2012)
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Conference Proceeding
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Lee, Dong Uk, Kim, Kyung Whan, Kim, Kwan Weon, Lee, Kang Seol, Byeon, Sang Jin, Kim, Jae Hwan, Cho, Jin Hee, Lee, Jaejin, Chun, Jun Hyun
Published in IEEE journal of solid-state circuits (01.01.2015)
Published in IEEE journal of solid-state circuits (01.01.2015)
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Journal Article
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology
Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application
Jabeom Koo, Gil-su Kim, Junyoung Song, Kwan-Weon Kim, Young Jung Choi, Chulwoo Kim
Published in 2009 IEEE Custom Integrated Circuits Conference (01.09.2009)
Published in 2009 IEEE Custom Integrated Circuits Conference (01.09.2009)
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Conference Proceeding
A single-loop DLL using an OR-AND duty-cycle correction technique
Keun-Soo Song, Cheul-Hee Koo, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding
A low power and high performance robust digital delay locked loop against noisy environments
Hyun-Woo Lee, Won-Joo Yun, Jong-Jin Lee, Ki-Han Kim, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface
Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
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Conference Proceeding
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM
Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jin Hee Cho, Han Ho Jin, Sang Kyun Nam, Jaejin Lee, Jun Hyun Chun, Sungjoo Hong
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Circuits Digest of Technical Papers (01.06.2014)
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Conference Proceeding
A wide-range all-digital multiphase DLL with supply noise tolerance
Hyunsoo Chae, Dongsuk Shin, Kisoo Kim, Kwan-Weon Kim, Young Jung Choi, Chulwoo Kim
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
Published in 2008 IEEE Asian Solid-State Circuits Conference (01.11.2008)
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Conference Proceeding
A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM
Hyun-Woo Lee, Won-Joo Yun, Sin-Deok Kang, Hyung-Wook Moon, Seung-Wook Kwack, Dong-Uk Lee, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
Published in 2005 IEEE Asian Solid-State Circuits Conference (01.11.2005)
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Conference Proceeding
A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM
Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, Seung-Wook Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih, Ye-Seok Yang
Published in 2006 IEEE Asian Solid-State Circuits Conference (01.11.2006)
Published in 2006 IEEE Asian Solid-State Circuits Conference (01.11.2006)
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Conference Proceeding
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV
Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, Jang Hwan Cho, Ki Hun Kwon, Min Jeong Kim, Jaejin Lee, Kun Woo Park, Byongtae Chung, Sungjoo Hong
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01.02.2014)
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Conference Proceeding
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
Yun, Won-Joo, Lee, Hyun Woo, Shin, Dongsuk, Kang, Shin Deok, Yang, Ji Yeon, Lee, Hyeng Ouk, Lee, Dong Uk, Sim, Sujeong, Kim, Young Ju, Choi, Won Jun, Song, Keun Soo, Shin, Sang Hoon, Choi, Hyang Hwa, Moon, Hyung Wook, Kwack, Seung Wook, Lee, Jung Woo, Choi, Young Kyoung, Park, Nak Kyu, Kim, Kwan Weon, Choi, Young Jung, Ahn, Jin-Hong, Yang, Ye Seok
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01.02.2008)
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Conference Proceeding