Difference in thermodynamics between ferrite and martensite in the Fe-Ni system
Nakada, Nobuo, Kusunoki, Naoki, Kajihara, Masanori, Hamada, Junichi
Published in Scripta materialia (01.09.2017)
Published in Scripta materialia (01.09.2017)
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Journal Article
A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability
Hamamoto, T., Minami, Y., Shino, T., Kusunoki, N., Nakajima, H., Morikado, M., Yamada, T., Inoh, K., Sakamoto, A., Higashi, T., Fujita, K., Hatsuda, K., Ohsawa, T., Nitayama, A.
Published in IEEE transactions on electron devices (01.03.2007)
Published in IEEE transactions on electron devices (01.03.2007)
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Journal Article
Accurate Measurement of Silicide Specific Contact Resistivity by Cross Bridge Kelvin Resistor for 28 nm Complementary Metal--Oxide--Semiconductor Technology and Beyond
Ohuchi, Kazuya, Kusunoki, Naoki, Matsuoka, Fumitomo
Published in Japanese Journal of Applied Physics (01.04.2011)
Published in Japanese Journal of Applied Physics (01.04.2011)
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Journal Article
Accurate Measurement of Silicide Specific Contact Resistivity by Cross Bridge Kelvin Resistor for 28 nm Complementary Metal–Oxide–Semiconductor Technology and Beyond
Ohuchi, Kazuya, Kusunoki, Naoki, Matsuoka, Fumitomo
Published in Japanese Journal of Applied Physics (01.04.2011)
Published in Japanese Journal of Applied Physics (01.04.2011)
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Journal Article
TCAD Modeling of Carbon Electrode for Highly Accurate Reset Current Prediction of Phase Change Memory Considering Both Thermal and Electronic Transport
Tsukagoshi, Takayuki, Tokuhira, Hiroki, Nakai, Tsukasa, Matsuzawa, Yuya, Masuda, Ryouji, Furuhashi, Hironobu, Fujii, Shosuke, Ode, Hiroyuki, Kusunoki, Naoki
Published in 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (27.09.2023)
Published in 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (27.09.2023)
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Conference Proceeding
25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)
Hokazono, A, Itokawa, H, Kusunoki, N, Mizushima, I, Inaba, S, Kawanaka, S, Toyoshima, Y
Published in IEEE transactions on electron devices (01.05.2011)
Published in IEEE transactions on electron devices (01.05.2011)
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Journal Article
Source/drain engineering for MOSFETs with embedded-Si:C technology
Itokawa, Hiroshi, Yasutake, Nobuaki, Kusunoki, Naoki, Okamoto, Shintaro, Aoki, Nobutoshi, Mizushima, Ichiro
Published in Applied surface science (30.07.2008)
Published in Applied surface science (30.07.2008)
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Journal Article
Conference Proceeding
Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
Shino, T., Kusunoki, N., Higashi, T., Ohsawa, T., Fujita, K., Hatsuda, K., Ikumi, N., Matsuoka, F., Kajitani, Y., Fukuda, R., Watanabe, Y., Minami, Y., Sakamoto, A., Nishimura, J., Nakajima, M., Morikado, M., Inoh, K., Hamamoto, T., Nitayama, A.
Published in 2006 International Electron Devices Meeting (2006)
Published in 2006 International Electron Devices Meeting (2006)
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Conference Proceeding
A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology
Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
Conference Proceeding
A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond
Yasutake, Nobuaki, Azuma, Atsushi, Ishida, Tatsuya, Ohuchi, Kazuya, Aoki, Nobutoshi, Kusunoki, Naoki, Mori, Shinji, Mizushima, Ichiro, Morooka, Tetsu, Kawanaka, Shigeru, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.11.2007)
Published in Solid-state electronics (01.11.2007)
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Journal Article
Conference Proceeding
A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology
Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell
Shino, T., Ohsawa, T., Higashi, T., Fujita, K., Kusunoki, N., Minami, Y., Morikado, M., Nakajima, H., Inoh, K., Hamamoto, T., Nitayama, A.
Published in IEEE transactions on electron devices (01.10.2005)
Published in IEEE transactions on electron devices (01.10.2005)
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Journal Article
A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond
Yasutake, Nobuaki, Azuma, Atsushi, Ishida, Tatsuya, Ohuchi, Kazuya, Aoki, Nobutoshi, Kusunoki, Naoki, Mori, Shinji, Mizushima, Ichiro, Morooka, Tetsu, Kawanaka, Shigeru, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.11.2007)
Published in Solid-state electronics (01.11.2007)
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Journal Article