A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications
Tsai, Chih-Wei, Chiu, Yu-Ting, Tu, Yo-Hao, Cheng, Kuo-Hsing
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2021)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2021)
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Journal Article
Low supply voltage and multiphase all-digital crystal-less clock generator
Tu, Yo-Hao, Liu, Jen-Chieh, Cheng, Kuo-Hsing, Chang, Chi-Yang
Published in IET circuits, devices & systems (01.11.2018)
Published in IET circuits, devices & systems (01.11.2018)
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Journal Article
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes
Kuo-Hsing Cheng, Cheng-Liang Hung, Alex Gong, Cihun-Siyong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun
Published in IEEE transactions on circuits and systems. II, Express briefs (01.08.2014)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.08.2014)
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Journal Article
A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs
Tu, Yo-Hao, Liu, Jen-Chieh, Cheng, Kuo-Hsing, Hsu, Chih-Hsun
Published in Analog integrated circuits and signal processing (01.10.2017)
Published in Analog integrated circuits and signal processing (01.10.2017)
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Journal Article
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
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Conference Proceeding
A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver
JIANG, Shu-Yu, CHENG, Kuo-Hsing, JIAN, Pei-Yi
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2009)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2009)
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Journal Article
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop
Cheng, Kuo-Hsing, Yang, Wei-Bin, Ying, Cheng-Ming
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
Published in IEEE transactions on circuits and systems. 2, Analog and digital signal processing (01.11.2003)
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Journal Article