A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS
Kulkarni, Sarvesh H., Chen, Zhanping, Srinivasan, Balaji, Pedersen, Brian, Bhattacharya, Uddalak, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.04.2016)
Published in IEEE journal of solid-state circuits (01.04.2016)
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Journal Article
High performance level conversion for dual VDD design
KULKARNI, Sarvesh H, SYLVESTER, Dennis
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2004)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2004)
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Journal Article
A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process
Kulkarni, Sarvesh H., Ikram, Umaira, Bhatt, Kedar, Chao, Yu-Lin, Chang, Yao-Feng, Jenkins, Ian, Murari, Venkatesh, Thambithurai, David, Hasan, Mohammad, Li, Jiabo, Paulson, Leif R., Sell, Bernhard, Bhattacharya, Uddalak, Zhang, Ying
Published in IEEE solid-state circuits letters (2021)
Published in IEEE solid-state circuits letters (2021)
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Journal Article
A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
YIH WANG, HONG JO AHN, LIN, Jie-Feng, NG, Yong-Gee, POST, Ian, LIQIONG WEI, YING ZHANG, ZHANG, Kevin, BOHR, Mark, BHATTACHARYA, Uddalak, ZHANPING CHEN, COAN, Tom, HAMZAOGLU, Fatih, HAFEZ, Walid M, JAN, Chia-Hong, KOLAR, Pramod, KULKARNI, Sarvesh H
Published in IEEE journal of solid-state circuits (2008)
Published in IEEE journal of solid-state circuits (2008)
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Conference Proceeding
Journal Article
Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology
Chao, Yu-Lin, Su, Chen-Yi, Ramey, Stephen M., Bhattacharya, Uddalak, Sell, Bernhard, Zhang, Ying, Kulkarni, Sarvesh H., Cha, Soonwoo, Paulson, Leif R., Rajarshi, Salil M., Bloomstrom, Jason, Liu, Guannan, Armstrong, Mark, Li, Jiabo
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
A 0.9-μ² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming
Chen, Zhanping, Kulkarni, Sarvesh H, Dorgan, Vincent E, Salil Manohar Rajarshi, Jiang, Lei, Bhattacharya, Uddalak
Published in IEEE journal of solid-state circuits (01.01.2017)
Published in IEEE journal of solid-state circuits (01.01.2017)
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Journal Article
A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming
Zhanping Chen, Kulkarni, Sarvesh H., Dorgan, Vincent E., Rajarshi, Salil Manohar, Lei Jiang, Bhattacharya, Uddalak
Published in IEEE journal of solid-state circuits (01.04.2017)
Published in IEEE journal of solid-state circuits (01.04.2017)
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Journal Article
Power distribution techniques for dual VDD circuits
Kulkarni, Sarvesh H., Sylvester, Dennis
Published in Proceedings of the 2006 Asia and South Pacific Design Automation Conference (24.01.2006)
Published in Proceedings of the 2006 Asia and South Pacific Design Automation Conference (24.01.2006)
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Conference Proceeding
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 mu m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS
Kulkarni, Sarvesh H, Chen, Zhanping, He, Jun, Jiang, Lei, Pedersen, MBrian, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.04.2010)
Published in IEEE journal of solid-state circuits (01.04.2010)
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Journal Article
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 [Formula Omitted]m[Formula Omitted] 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS
Kulkarni, Sarvesh H, Chen, Zhanping, He, Jun, Jiang, Lei, Pedersen, M. Brian, Zhang, Kevin
Published in IEEE journal of solid-state circuits (01.04.2010)
Published in IEEE journal of solid-state circuits (01.04.2010)
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Journal Article
A new algorithm for improved VDD assignment in low power dual VDD systems
Kulkarni, Sarvesh H., Srivastava, Ashish N., Sylvester, Dennis
Published in International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design; 09-11 Aug. 2004 (09.08.2004)
Published in International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design; 09-11 Aug. 2004 (09.08.2004)
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Conference Proceeding
Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements
Bhattacharya, Uddalak, Kulkarni, Sarvesh H, Dorgan, Vincent E, Chao, Yu-Lin
Year of Publication 22.08.2023
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Year of Publication 22.08.2023
Patent
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET) AS ANTIFUSE ELEMENTS
DORGAN, Vincent E, BHATTACHARYA, Uddalak, KULKARNI, Sarvesh H, CHAO, Yu-Lin
Year of Publication 10.02.2022
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Year of Publication 10.02.2022
Patent