Search Results - "Koh, Risho" :: K.UTB vyhledávací portál

Loading…

Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET

by Risho Koh, Risho Koh
Published in Japanese Journal of Applied Physics (01.04.1999)

Get full text

Journal Article

Loading…

Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 µm Small Logic Swing Operation

by Risho Koh, Risho Koh
Published in Japanese Journal of Applied Physics (01.04.1998)

Get full text

Journal Article

Loading…

Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs

by Koh, Risho
Published in Japanese Journal of Applied Physics (2000)

Get full text

Journal Article

Loading…

Parameter Extraction and Comparison of Self-Heating Models for Power MOSFETs Based on Transient Current Measurements : ADVANCED MODELING OF POWER DEVICES AND THEIR APPLICATIONS

by KOH, Risho, IIZUKA, Takahiro
Published in IEEE transactions on electron devices (2013)

Get full text

Journal Article

Loading…

Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 µm Fully Depleted SOI-MOSFET

by Risho Koh, Risho Koh, Hiroshi Matsumoto, Hiroshi Matsumoto
Published in Japanese Journal of Applied Physics (01.03.1997)

Get full text

Journal Article

Loading…

Parameter Extraction and Comparison of Self-Heating Models for Power MOSFETs Based on Transient Current Measurements

by Koh, R., Iizuka, T.
Published in IEEE transactions on electron devices (01.02.2013)

Get full text

Journal Article

Loading…

A SPICE-compatible model of SG-MONOS for 28nm flash macro design considering the parasitic resistance caused by trapped charges

by Koh, Risho, Miyamori, Mitsuru, Tsuneno, Katsumi, Muta, Tetsuya, Kawashima, Yoshiyuki
Published in 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (01.09.2017)

Get full text

Conference Proceeding

Loading…

Capacitance network model of the short channel effect for 0.1 μm fully depleted SOI MOSFET

by KOH, R, KATO, H, MATSUMOTO, H
Published in Japanese journal of applied physics (01.02.1996)

Get full text

Conference Proceeding

Loading…

An Investigation on the Short Channel Effect for 0.1 µm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model

by Koh, Risho, Haruo Kato, Haruo Kato
Published in Japanese Journal of Applied Physics (01.02.1995)

Get full text

Journal Article

Loading…

Capacitance Network Model of the Short Channel Effect for 0.1 µm Fully Depleted SOI MOSFET

by Koh, Risho, Kato, Haruo, Hiroshi Matsumoto, Hiroshi Matsumoto
Published in Japanese Journal of Applied Physics (01.02.1996)

Get full text

Journal Article

Loading…

Self-heating parameter extraction of power MOSFETs based on transient drain current measurements and on the 2-cell self-heating model

by Koh, R., Iizuka, T.
Published in 2012 IEEE International Conference on Microelectronic Test Structures (01.03.2012)

Get full text

Conference Proceeding

Loading…

Surface-enhanced Raman scattering from surface layers of gas-evaporated silver small particles

by HAYASHI, S, KOH, R, YAMAMOTO, K, ISHIDA, H
Published in Japanese Journal of Applied Physics (01.08.1989)

Get full text

Journal Article

Loading…

A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

by Takeuchi, K., Koh, R., Mogami, T.
Published in IEEE transactions on electron devices (01.09.2001)

Get full text

Journal Article

Loading…

Accurate spice modeling of 80V power LDMOS with interdigitated source structure

by Tamegaya, Y., Koh, R., Hatanaka, Y., Iizuka, T.
Published in 2012 24th International Symposium on Power Semiconductor Devices and ICs (01.06.2012)

Get full text

Conference Proceeding

Loading…

FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME

by TAKEUCHI, KIYOSHI, KOH, RISHO, TANAKA, KATSUHIKO
Year of Publication 11.08.2005

Get full text

Patent

Loading…

FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME

by TAKEUCHI, KIYOSHI, KOH, RISHO, TANAKA, KATSUHIKO
Year of Publication 11.08.2005

Get full text

Patent

Loading…

Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

by Chenyue Ma, Mattausch, Hans Jurgen, Matsuzawa, Kazuya, Yamaguchi, Seiichiro, Hoshida, Teruhiko, Imade, Masahiro, Koh, Risho, Arakawa, Takahiko, Miura-Mattausch, Mitiko
Published in IEEE transactions on device and materials reliability (01.09.2014)

Get full text

Magazine Article