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80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
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Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)
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Year of Publication 26.02.2001
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Year of Publication 30.01.2020
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Year of Publication 30.01.2020
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