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Published in Journal of crystal growth (01.01.1978)
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A low-impedance open-bitline array for multigigabit DRAM
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Published in IEEE journal of solid-state circuits (01.04.2002)
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A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme
Tanaka, H., Aoki, M., Sakata, T., Kimura, S., Sakashita, N., Hidaka, H., Tachibana, T., Kimura, K.
Published in IEEE journal of solid-state circuits (01.08.1999)
Published in IEEE journal of solid-state circuits (01.08.1999)
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Year of Publication 07.06.2001
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SEMICONDUCTOR DEVICE
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Year of Publication 31.08.2000
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Year of Publication 31.08.2000
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A multigigabit DRAM technology with 6F(2) open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
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Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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Year of Publication 30.08.2001
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Year of Publication 30.08.2001
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Dynamic RAM and semiconductor device
TAKAHASHI TSUGIO, KAJIKAYA KAZUHIKO, KIMURA KATSUTAKA, SEKIGUCHI TOMONORI, NAKAMURA YOSHITAKA, TAKEMURA RIICHIRO
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Year of Publication 15.06.2001
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PRODUCTION AND OPERATION METHOD THEREOF
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Year of Publication 16.04.2001
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INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
KURE, TOKUO, SAEKI, SHUNICHI, KURATA, HIDEAKI, GOTO, YASUSHI, KIMURA, KATSUTAKA, KOBAYASHI, TAKASHI, KUME, HITOSHI
Year of Publication 22.03.2001
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Year of Publication 22.03.2001
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SEMICONDCUCTOR MEMORY DEVICE WITH CMOS SENSE AMPLIFIER
ETOH, JUN, KAWAJIRI, YOSHIKI, ITOH, KIYO, KIMURA, KATSUTAKA, HORI, RYOICHI
Year of Publication 04.04.1994
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Year of Publication 04.04.1994
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FERROELECTRIC MEMORY
SAKATA, TAKESHI, SEKIGUCHI, TOMONORI, FUJISAWA, HIROKI, KIMURA, KATSUTAKA, ISODA, MASANORI, KAJIGAYA, KAZUHIKO
Year of Publication 04.09.1997
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Year of Publication 04.09.1997
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