Role of Nitric Oxide as Mediator of Nerve Injury in Inflammatory Neuropathies
Lehmann, Helmar C, Köhne, Angelika, Meyer zu Hörste, Gerd, Dehmel, Thomas, Kiehl, Olivia, Hartung, Hans-Peter, Kastenbauer, Stefan, Kieseier, Bernd C
Published in Journal of neuropathology and experimental neurology (01.04.2007)
Published in Journal of neuropathology and experimental neurology (01.04.2007)
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Journal Article
Transmission gate delay models for circuit optimization
Eisele, V., Hoppe, B., Kiehl, O.
Published in Proceedings of the European Design Automation Conference, 1990., EDAC (1990)
Published in Proceedings of the European Design Automation Conference, 1990., EDAC (1990)
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Conference Proceeding
Metalloproteinases as mediators of tissue regeneration in the peripheral nerve: an important role for metalloproteinase-2
Köhne, A, Lehmann, HC, Kiehl, O, Meyer zu Hörste, G, Hartung, HP, Kieseier, BC
Published in Aktuelle Neurologie (11.09.2007)
Published in Aktuelle Neurologie (11.09.2007)
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Conference Proceeding
A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
Kirihata, T., Gall, M., Hosokawa, K., Dortu, J.-M., Hing Wong, Pfefferi, P., Ji, B.L., Weinfurtner, O., DeBrosse, J.K., Terletzki, H., Selz, M., Ellis, W., Wordeman, M.R., Kiehl, O.
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
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Journal Article
A 220-mm(2), four-and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture
Kirihata, T, Gall, M, Hosokawa, K, Dortu, J-M, Wong, Hing, Pfefferi, P, Ji, B L, Weinfurtner, O, DeBrosse, J K, Terletzki, H, Selz, M, Ellis, W, Wordeman, M R, Kiehl, O
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
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Journal Article
220 mm super(2) 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
Kirihata, T, Gall, M, Hosokawa, K, Dortu, J-M, Wong, H, Pfefferl, K-P, Ji, B, Weinfurtner, O, DeBrosse, J, Terletzki, H, Selz, M, Ellis, W, Wordeman, M, Kiehl, O
Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
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Published in Digest of technical papers - IEEE International Solid-State Circuits Conference (01.01.1998)
Journal Article
A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture
Kirihata, T., Mueller, G., Clinton, M., Loeffler, S., Ji, B., Terletzki, H., Hanson, D., Chorng-Lil Hwang, Lehmann, G., Storaska, D., Daniel, G., Hsu, L., Weinfurtner, O., Boehler, T., Schnell, J., Frankowsky, G., Netis, D., Ross, J., Reith, A., Kiehl, O., Wordeman, M.
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
Published in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (2001)
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Conference Proceeding
A 220 mm/sup 2/ 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
Kirihata, T., Gall, M., Hosokawa, K., Dortu, J.-M., Wong, H., Pfefferl, K.-P., Ji, B., Weinfurtner, O., DeBrosse, J., Terletzki, H., Selz, M., Ellis, W., Wordeman, M., Kiehl, O.
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
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Conference Proceeding