Perpetuality and Uniform Normalization in Orthogonal Rewrite Systems
Khasidashvili, Zurab, Ogawa, Mizuhito, van Oostrom, Vincent
Published in Information and computation (10.01.2001)
Published in Information and computation (10.01.2001)
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Journal Article
An enhanced cut-points algorithm in formal equivalence verification
Khasidashvili, Z., Moondanos, J., Kaiss, D., Hanna, Z.
Published in Sixth IEEE International High-Level Design Validation and Test Workshop (2001)
Published in Sixth IEEE International High-Level Design Validation and Test Workshop (2001)
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Conference Proceeding
Symbolic trajectory evaluation for word-level verification: theory and implementation
Chakraborty, Supratik, Khasidashvili, Zurab, Seger, Carl-Johan H., Gajavelly, Rajkumar, Haldankar, Tanmay, Chhatani, Dinesh, Mistry, Rakesh
Published in Formal methods in system design (01.06.2017)
Published in Formal methods in system design (01.06.2017)
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Journal Article
Simultaneous SAT-Based Model Checking of Safety Properties
Khasidashvili, Zurab, Nadel, Alexander, Palti, Amit, Hanna, Ziyad
Published in Hardware and Software, Verification and Testing (2006)
Published in Hardware and Software, Verification and Testing (2006)
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Book Chapter
Conference Proceeding
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints
Khasidashvili, Z., Skaba, M., Kaiss, D., Hanna, Z.
Published in IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 (07.11.2004)
Published in IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 (07.11.2004)
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Conference Proceeding
Relating conflict-free stable transition and event models via redex families
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Journal Article
Conference Proceeding
Preprocessing techniques for first-order clausification
Hoder, Krystof, Khasidashvili, Z., Korovin, K., Voronkov, A.
Published in 2012 Formal Methods in Computer-Aided Design (FMCAD) (01.10.2012)
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Published in 2012 Formal Methods in Computer-Aided Design (FMCAD) (01.10.2012)
Conference Proceeding
Verifying equivalence of memories using a first order logic theorem prover
Khasidashvili, Z., Kinanah, M., Voronkov, A.
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
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Conference Proceeding
A compositional theory for post-reboot observational equivalence checking of hardware
Khasidashvili, Z., Kaiss, D., Bustan, D.
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
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Conference Proceeding
Assume-guarantee validation for STE properties within an SVA environment
Khasidashvili, Z., Gavrielov, G., Melham, T.
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
Published in 2009 Formal Methods in Computer-Aided Design (01.11.2009)
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Conference Proceeding
Post-reboot Equivalence and Compositional Verification of Hardware
Khasidashvili, Z., Skaba, M., Kaiss, D., Hanna, Z.
Published in 2006 Formal Methods in Computer Aided Design (01.11.2006)
Published in 2006 Formal Methods in Computer Aided Design (01.11.2006)
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Conference Proceeding