A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
Klim, P.J., Barth, J., Reohr, W.R., Dick, D., Fredeman, G., Koch, G., Le, H.M., Khargonekar, A., Wilcox, P., Golz, J., Kuang, J.B., Mathews, A., Law, J.C., Luong, T., Ngo, H.C., Freese, R., Hunter, H.C., Nelson, E., Parries, P., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
Klim, P., Barth, J., Reohr, W., Dick, D., Fredeman, G., Koch, G., Hien Le, Khargonekar, A., Wilcox, P., Golz, J., Kuang, J.B., Mathews, A., Trong Luong, Hung Ngo, Freese, R., Hunter, H., Nelson, E., Parries, P., Kirihata, T., Iyer, S.
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
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Conference Proceeding