A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
Mansuri, Mozhgan, Jaussi, James E., Kennedy, Joseph T., Tzu-Chien Hsueh, Shekhar, Sudip, Balamurugan, Ganesh, O'Mahony, Frank, Roberts, Clark, Mooney, Randy, Casper, Bryan
Published in IEEE journal of solid-state circuits (01.12.2013)
Published in IEEE journal of solid-state circuits (01.12.2013)
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Journal Article
Conference Proceeding
광학 적용을 위한 폴리실록산 제형 및 코팅, 이의 제조 방법, 및 용도
IWAMOTO NANCY E, VARAPRASAD DESARAJU, KENNEDY JOSEPH T, MUKHOPADHYAY SUDIP, XIE SONGYUAN
Year of Publication 26.10.2018
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Year of Publication 26.10.2018
Patent
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS
Mansuri, M., Jaussi, J. E., Kennedy, J. T., Hsueh, T., Shekhar, S., Balamurugan, G., O'Mahony, F., Roberts, C., Mooney, R., Casper, B.
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01.02.2013)
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Conference Proceeding