A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS
Iwata, K., Mochizuki, S., Kimura, M., Shibayama, T., Izuhara, F., Ueda, H., Hosogi, K., Nakata, H., Ehama, M., Kengaku, T., Nakazawa, T., Watanabe, H.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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A dual-issue RISC processor for multimedia signal processing
Sato, H., Holmann, E., Yoshida, T., Matsuo, M., Kengaku, T.
Published in 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (1997)
Published in 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (1997)
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A macrocell approach for VLSI processor design
Tokuda, T., Korematsu, J., Shimazu, Y., Sakashita, N., Kengaku, T., Fugiyama, T., Ohno, T., Tomisawa, O.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.12.1988)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.12.1988)
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Michael addition in the pseudoliquid phase of heteropoly compounds
Kengaku, Toko, Matsumoto, Youichi, Na, Kyutae, Misono, Makoto
Published in Journal of molecular catalysis. A, Chemical (15.09.1998)
Published in Journal of molecular catalysis. A, Chemical (15.09.1998)
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A 256mW full-HD H.264 high-profile CODEC featuring dual macroblock-pipeline architecture in 65nm CMOS
Iwata, K., Mochizuki, S., Shibayama, T., Izuhara, F., Ueda, H., Hosogi, K., Nakata, H., Ehama, M., Kengaku, T., Nakazawa, T., Watanabe, H.
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
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Conference Proceeding
Built-in self-test in a 24 bit floating point digital signal processor
Sakashita, N., Sawai, H., Teraoka, E., Fujiyama, T., Kengaku, T., Shimazu, Y., Tokuda, T.
Published in Proceedings. International Test Conference 1990 (1990)
Published in Proceedings. International Test Conference 1990 (1990)
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A built-in self-test for ADC and DAC in a single-chip speech CODEC
Teraoka, E., Kengaku, T., Yasui, I., Ishikawa, K., Matsuo, T., Wakada, H., Sakashita, N., Shimazu, Y., Tokuda, T.
Published in Designing, testing, and diagnostics--join them : International Test Conference 1993 proceedings :October 17-21, 1993, Convention Center, Baltimore, Maryland, USA (1993)
Published in Designing, testing, and diagnostics--join them : International Test Conference 1993 proceedings :October 17-21, 1993, Convention Center, Baltimore, Maryland, USA (1993)
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Journal Article
A 50 MHz 24 b floating-point DSP
Shimazu, Y., Kengaku, T., Fujiyama, T., Teraoka, E., Ohno, T., Tokuda, T., Tomisawa, O., Tsujimichi, S.
Published in IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers (1989)
Published in IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers (1989)
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Conference Proceeding
A 1.8 V 36 mW DSP for the half-rate speech codec
Shiraishi, T., Kawamoto, K., Ishikawa, K., Sato, H., Asai, F., Teraoka, E., Kengaku, T., Takata, H., Tokuda, T., Nishida, K., Saitoh, K.
Published in Proceedings of Custom Integrated Circuits Conference (1996)
Published in Proceedings of Custom Integrated Circuits Conference (1996)
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