Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers
Faxing Che, Li, H. Y., Xiaowu Zhang, Shan Gao, Teo, K. H.
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.06.2012)
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01.06.2012)
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Journal Article
Intuitive and inexpensive method to evaluate flip chip bonding parameters of micro bump with wafer-level underfill material using glass substrate
Jie Li Aw, Ser Choong Chong, Cereno, Daniel Ismael, KengHwa Teo, Rao, Vempati Srinivasa
Published in 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) (01.12.2013)
Published in 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) (01.12.2013)
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Conference Proceeding