Search Results - "Kedar, Dhori" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

by Weber, Olivier, Min, Doohong, Villaret, Alexandre, Park, Jinha, Lee, Ilmin, Vandenbossche, Eric, Kim, Dohun, Yun, Jiyoung, Park, Jinwoo, Lee, Minuk, Kang, Jinseok, Lee, Hyunjong, Choi, Youngju, Kim, Inhwan, Kim, Joochan, Kedar, Dhori, Janardan, Dhori Kedar, Haendler, Sebastien, Elghouli, Salim, Puget, Sophie, Bernicot, Christophe, Bernard, Emilie, Wacquant, Francois, Nimsgern, Fabien, Choi, Joonhyuk, Maeda, Shigenobu, Lee, Jongho, Arnaud, Franck
Published in 2022 International Electron Devices Meeting (IEDM) (03.12.2022)

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Conference Proceeding

Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

by Dhori, Kedar Janardan, Kumar, Vinay, Rawat, Harsh
Published in IEEE transactions on very large scale integration (VLSI) systems (01.11.2014)

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Journal Article

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS

by Srivastav, Mukesh Kumar, Rimjhim, Mishra, Roshan, Grover, Anuj, Dhori, Kedar Janardan, Rawat, Harsh
Published in 2022 IEEE International Symposium on Circuits and Systems (ISCAS) (28.05.2022)

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Conference Proceeding

Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI

Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI

by Kumar, Chandan, Kumar, Rahul, Grove, Anuj, Chatterjee, Shouri, Dhori, Kedar Janardan, Rawat, Harsh
Published in 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID) (01.02.2022)

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Conference Proceeding

40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode

40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode

by Dhori, Kedar Janardan, Kumar, Promod, Lecocq, Christophe, Urard, Pascal, Callen, Olivier, Cacho, Florian, Parra, Maryline, Pandey, Prashant, Noblet, Daniel
Published in 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID) (01.02.2022)

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Conference Proceeding

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies

by Clerc, Sylvain, Dhori, Kedar Janardan, Wilson, Robin M., Goel, Rohit, Marchal, Sebastien, Pourchon, Franck, Dutto, Christian, Gomez, Ricardo Gomez
Published in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (13.09.2021)

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Conference Proceeding

A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM

A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM

by Dhori, Kedar Janardan, Kumar, Vinay, Kumar, Ashish
Published in 2015 28th International Conference on VLSI Design (01.01.2015)

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Conference Proceeding

High-yield design of high-density SRAM for low-voltage and low-leakage operations

High-yield design of high-density SRAM for low-voltage and low-leakage operations

by Dhori, Kedar Janardan, Chawla, Hitesh, Kumar, Ashish, Pandey, Prashant, Kumar, Promod, Ciampolini, Lorenzo, Cacho, Florian, Croain, Damien
Published in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2017)

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Conference Proceeding

A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation

A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation

by Kumar, Ashish, Kumar, Vinay, Janardan, Dhori Kedar, Visweswaran, G. S., Saha, Kaushik
Published in 2015 International Conference on IC Design & Technology (ICICDT) (01.06.2015)

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Conference Proceeding

CIRCUITRY FOR ADJUSTING RETENTION VOLTAGE OF A STATIC RANDOM ACCESS MEMORY (SRAM)

CIRCUITRY FOR ADJUSTING RETENTION VOLTAGE OF A STATIC RANDOM ACCESS MEMORY (SRAM)

by DHORI, Kedar Janardan
Year of Publication 28.04.2022

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Patent

DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS

DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS

by DHORI, Kedar Janardan
Year of Publication 21.04.2022

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Patent

LOWER POWER MEMORY WRITE OPERATION

LOWER POWER MEMORY WRITE OPERATION

by DHORI, Kedar Janardan
Year of Publication 21.10.2021

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Patent

SRAM CELL LAYOUT INCLUDING ARRANGEMENT OF MULTIPLE ACTIVE REGIONS AND MULTIPLE GATE REGIONS

SRAM CELL LAYOUT INCLUDING ARRANGEMENT OF MULTIPLE ACTIVE REGIONS AND MULTIPLE GATE REGIONS

by JANARDAN, Dhori Kedar, AHMED, Shafquat Jahan
Year of Publication 14.12.2023

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Patent

SRAM cell layout including arrangement of multiple active regions and multiple gate regions

SRAM cell layout including arrangement of multiple active regions and multiple gate regions

by Dhori, Kedar Janardan, Ahmed, Shafquat Jahan
Year of Publication 12.09.2023

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Patent

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder

by Singh, Shivendra, Gupta, Varshita, Grover, Anuj, Dhori, Kedar Janardhan
Published in 2020 21st International Symposium on Quality Electronic Design (ISQED) (01.03.2020)

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Conference Proceeding

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS

by Srivastav, Mukesh Kumar, Rimjhim, Soni, Govind, Mittal, Umang, Tewari, Rupali, Yadav, Riya, Grover, Anuj, Dhori, Kedar Janardan, Rawat, Harsh
Published in 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (28.11.2021)

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Conference Proceeding

SRAM LAYOUT WITH SMALL FOOTPRINT AND EFFICIENT ASPECT RATIO

SRAM LAYOUT WITH SMALL FOOTPRINT AND EFFICIENT ASPECT RATIO

by AHMED, Shafquat Jahan, DHORI, Kedar Janardan
Year of Publication 24.06.2021

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Patent

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

by Chawla, Nitin, Rawat, Harsh, Dhori, Kedar Janardan, Ayodhyawasi, Manuj, Kumar, Promod
Year of Publication 10.09.2024

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Patent

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

by CHAWLA, Nitin, KUMAR, Promod, AYODHYAWASI, Manuj, DHORI, Kedar Janardan, RAWAT, Harsh
Year of Publication 28.08.2024

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Patent

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM)

by CHAWLA, Nitin, KUMAR, Promod, AYODHYAWASI, Manuj, DHORI, Kedar Janardan, RAWAT, Harsh
Year of Publication 28.08.2024

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Patent

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