Mechanism of Contact Resistance Reduction in Nickel Silicide Films by Pt Incorporation
Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Kawanaka, S., Inaba, S., Toyoshima, Y.
Published in IEEE transactions on electron devices (01.11.2011)
Published in IEEE transactions on electron devices (01.11.2011)
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In situ Doped Embedded-SiGe Source/Drain Technique for 32 nm Node p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor
Okamoto, Hiroki, Hokazono, Akira, Adachi, Kanna, Yasutake, Nobuaki, Itokawa, Hiroshi, Okamoto, Shintaro, Kondo, Masaki, Tsujii, Hideji, Ishida, Tatsuya, Aoki, Nobutoshi, Fujiwara, Makoto, Kawanaka, Shigeru, Azuma, Atsushi, Toyoshima, Yoshiaki
Published in Japanese Journal of Applied Physics (01.04.2008)
Published in Japanese Journal of Applied Physics (01.04.2008)
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Journal Article
STORAGE DEVICE
NOMURA YUKIHIRO, KAMATA YOSHIKI, KAWANAKA SHIGERU, TAKASHIMA DAIZABURO, ASAO YOSHIAKI, IIZUKA TAKAHIKO, MOROTA MISAKO
Year of Publication 24.03.2023
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Year of Publication 24.03.2023
Patent
Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation
Kukita, Kentaro, Uechi, Tadayoshi, Shimokawa, Junji, Goto, Masakazu, Yokota, Yoshinori, Kawanaka, Shigeru, Tanamoto, Tetsufumi, Tanimoto, Hiroyoshi, Takagi, Shinichi
Published in Japanese Journal of Applied Physics (01.04.2018)
Published in Japanese Journal of Applied Physics (01.04.2018)
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Journal Article
25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)
Hokazono, A, Itokawa, H, Kusunoki, N, Mizushima, I, Inaba, S, Kawanaka, S, Toyoshima, Y
Published in IEEE transactions on electron devices (01.05.2011)
Published in IEEE transactions on electron devices (01.05.2011)
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Journal Article
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
GOTO MASAKAZU, KAWANAKA SHIGERU, SOTOZONO AKIRA, KONDO YOSHIYUKI, OGURO TATSUYA
Year of Publication 27.10.2014
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Year of Publication 27.10.2014
Patent
Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ Atomic level analysis of Pt/B/As distribution within silicide films
Sonehara, T., Hokazono, A., Akutsu, H., Sasaki, T., Uchida, H., Tomita, M., Tsujii, H., Kawanaka, S., Inaba, S., Toyoshima, Y.
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
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Conference Proceeding
(Invited) Quantitative Correlation Between Low-Field Mobility and High-Field Carrier Velocity in Quasi-Ballistic-Transport MISFETs with High-k Gate Dielectrics
Tatsumura, Kosuke, Goto, Masakazu, Kawanaka, Shigeru, Kinoshita, Atsuhiro
Published in ECS transactions (01.01.2010)
Published in ECS transactions (01.01.2010)
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Journal Article
A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology
Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
Conference Proceeding
A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond
Yasutake, Nobuaki, Azuma, Atsushi, Ishida, Tatsuya, Ohuchi, Kazuya, Aoki, Nobutoshi, Kusunoki, Naoki, Mori, Shinji, Mizushima, Ichiro, Morooka, Tetsu, Kawanaka, Shigeru, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.11.2007)
Published in Solid-state electronics (01.11.2007)
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Journal Article
Conference Proceeding
A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology
Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Journal Article
A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications
Nii, H, Yamada, T, Inoh, K, Shino, T, Kawanaka, S, Yoshimi, M, Katsumata, Y
Published in IEEE transactions on electron devices (01.07.2000)
Published in IEEE transactions on electron devices (01.07.2000)
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Journal Article
A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond
Yasutake, Nobuaki, Azuma, Atsushi, Ishida, Tatsuya, Ohuchi, Kazuya, Aoki, Nobutoshi, Kusunoki, Naoki, Mori, Shinji, Mizushima, Ichiro, Morooka, Tetsu, Kawanaka, Shigeru, Toyoshima, Yoshiaki
Published in Solid-state electronics (01.11.2007)
Published in Solid-state electronics (01.11.2007)
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Journal Article
Memory device
Iizuka, Takahiko, Kawanaka, Shigeru, Kamata, Yoshiki, Morota, Misako, Asao, Yoshiaki, Nomura, Yukihiro, Takashima, Daisaburo
Year of Publication 02.04.2024
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Year of Publication 02.04.2024
Patent
A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology
Fuse, T, Ohta, M, Tokumasu, M, Fujii, H, Kawanaka, S, Kameyama, A
Published in IEEE journal of solid-state circuits (01.02.2003)
Published in IEEE journal of solid-state circuits (01.02.2003)
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