Search Results - "Kavicharan, Mummaneni" :: K.UTB vyhledávací portál

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A Review on a Negative Capacitance Field-Effect Transistor for Low-Power Applications

by Malvika, Choudhuri, Bijit, Mummaneni, Kavicharan
Published in Journal of electronic materials (01.03.2022)

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A non-uniform silicon TFET design with dual-material source and compressed drain

by Talukdar, Jagritee, Mummaneni, Kavicharan
Published in Applied physics. A, Materials science & processing (2020)

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Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

by Talukdar, Jagritee, Choudhuri, Bijit, Mummaneni, Kavicharan
Published in Applied physics. A, Materials science & processing (2021)

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Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

by Kavicharan, Mummaneni, Murthy, Nukala Suryanarayana, Rao, Nistala Bheema, Prathima, Addanki
Published in Circuits, systems, and signal processing (01.09.2016)

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Dielectrically Modulated Single and Double Gate Tunnel FET Based Biosensors for Enhanced Sensitivity

by Talukdar, Jagritee, Rawat, Gopal, Mummaneni, Kavicharan
Published in IEEE sensors journal (01.12.2021)

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Temperature analysis of lead zirconate titanate GAA-NCFET nanowire with interface trap charges

by Kumar, Vivek, Maurya, Ravindra Kumar, Mummaneni, Kavicharan
Published in Materials science & engineering. B, Solid-state materials for advanced technology (01.09.2024)

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Highly sensitivity Non-Uniform Tunnel FET based biosensor using source engineering

by Talukdar, Jagritee, Rawat, Gopal, Mummaneni, Kavicharan
Published in Materials science & engineering. B, Solid-state materials for advanced technology (01.07.2023)

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Sensitivity and reliability assessment of pocket doped NCFET based dielectrically modulated biosensor considering steric hindrance effects

by Malvika, Talukdar, Jagritee, Choudhuri, Bijit, Mummaneni, Kavicharan
Published in Physica scripta (01.10.2024)

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A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature

by Talukdar, Jagritee, Mummaneni, Kavicharan
Published in SILICON (01.06.2022)

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A Novel Extended Source TFET with δp+- SiGe Layer

by Talukdar, Jagritee, Rawat, Gopal, Mummaneni, Kavicharan
Published in SILICON (01.10.2020)

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Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature

by Malvika, Talukdar, Jagritee, Choudhuri, Bijit, Mummaneni, Kavicharan
Published in Microelectronics and reliability (01.01.2024)

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N-DIBL optimization of NC-GAAFET NW for low power fast switching applications

by Kumar, Vivek, Maurya, Ravindra Kumar, Mummaneni, Kavicharan
Published in Microelectronics (01.09.2024)

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Noise behavior and reliability analysis of non-uniform body tunnel FET with dual material source

by Talukdar, Jagritee, Rawat, Gopal, Mummaneni, Kavicharan
Published in Microelectronics and reliability (01.04.2022)

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A new pocket-doped NCFET for low power applications: Impact of ferroelectric and oxide thickness on its performance

by Malvika, Choudhuri, Bijit, Mummaneni, Kavicharan
Published in Micro and nanostructures (2022) (01.09.2022)

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Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

by Talukdar, Jagritee, Rawat, Gopal, Singh, Kunal, Mummaneni, Kavicharan
Published in Journal of electronic materials (01.07.2020)

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Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET

by Talukdar, Jagritee, Rawat, Gopal, Mummaneni, Kavicharan
Published in Materials science in semiconductor processing (01.05.2022)

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Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

by Kumar, Vivek, Maurya, Ravindra Kumar, Malvika, Rawat, Gopal, Mummaneni, Kavicharan
Published in Physica scripta (01.11.2023)

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Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I on/I off

by Kumar, Vivek, Maurya, Ravindra Kumar, Malvika, Rawat, Gopal, Mummaneni, Kavicharan
Published in Semiconductor science and technology (01.05.2023)

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Source engineered TFET for digital inverters application

by Talukdar, Jagritee, Malvika, Das, Basab, Rawat, Gopal, Mummaneni, Kavicharan
Published in Physica scripta (01.04.2024)

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Optimal segmentation of Cu–CNT interconnects

by Seshasai, K., Sathyakam, P. Uma, Mummaneni, Kavicharan
Published in Multiscale and Multidisciplinary Modeling, Experiments and Design (01.09.2024)

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