Three-Dimensional Observation of Edge-Roughness on Poly-Si/TiN Stacked Gate Using Three-Dimensional STEM
Ono, S, Yamane, M, Katakami, A, Yugami, J, Koguchi, M, Ogasawara, M, Miyakawa, M, Kakibayashi, H, Ohji, Y
Published in Microscopy and microanalysis (01.07.2009)
Published in Microscopy and microanalysis (01.07.2009)
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Journal Article
High drive current NMOS with Si-SiGe heterostructure low electric field channel
Shima, M., Hatada, A., Shimamune, Y., Katakami, A., Hori, M., Kojima, M., Kase, M., Hashimoto, K., Mishima, Y., Nakamura, S.
Published in IEEE electron device letters (01.10.2004)
Published in IEEE electron device letters (01.10.2004)
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Journal Article
Visualization of high speed air flow by the spark tracing method with radiant trail
Ninomiya, N., Akiyama, M., Sugiyama, H., Katakami, A.
Published in Journal of visualization (01.12.2004)
Published in Journal of visualization (01.12.2004)
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Journal Article
A highly robust SiGe source drain technology realized by disposable sidewall spacer (DSW) for 65nm node and beyond
Kim, Y.S., Mori, T., Hayami, Y., Yamamoto, T., Morioka, H., Kokura, H., Kawamura, K., Shimamune, Y., Katakami, A., Hatada, A., Shima, M., Tamura, N., Ohta, H., Sakuma, T., Kojima, M., Nakaishi, M., Sugii, T., Miyajima, M.
Published in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 (2005)
Published in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 (2005)
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Conference Proceeding
Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs
Goto, K., Satoh, S., Ohta, H., Fukuta, S., Yamamoto, T., Mori, T., Tagawa, Y., Sakuma, T., Saiki, T., Shimamune, Y., Katakami, A., Hatada, A., Morioka, H., Hayami, Y., Inagaki, S., Kawamura, K., Kim, Y., Kokura, H., Tamura, N., Horiguchi, N., Kojima, M., Sugii, T., Hashimoto, K.
Published in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 (2004)
Published in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 (2004)
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Conference Proceeding
Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- [Formula Omitted] FETs
Ootsuka, F, Katakami, A, Shirai, K, Watanabe, T, Nakata, H, Kitajima, M, Aoyama, T, Eimori, T, Nara, Y, Ohji, Y, Tanjyo, M
Published in IEEE transactions on electron devices (01.04.2008)
Published in IEEE transactions on electron devices (01.04.2008)
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Journal Article
Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs
Ootsuka, F., Katakami, A., Shirai, K., Watanabe, T., Nakata, H., Kitajima, M., Aoyama, T., Eimori, T., Nara, Y., Ohji, Y., Tanjyo, M.
Published in IEEE transactions on electron devices (01.04.2008)
Published in IEEE transactions on electron devices (01.04.2008)
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Journal Article
Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology
Yamamoto, T., Kubo, T., Sukegawa, T., Katakami, A., Shimamune, Y., Tamura, N., Ohta, H., Miyashita, T., Sato, S., Kase, M., Sugii, T.
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
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Conference Proceeding
Technology Breakthrough of Low Temperature, Low Defect, and Low Cost SiGe Selective Epitaxial Growth (L3 SiGe SEG) Process for 45nm Node and Beyond
Shimamune, Y., Fukuda, M., Koiizuka, M., Katakami, A., Hatada, A., Ikeda, K., Kim, Y., Kawamura, K., Tamura, N., Mori, T., Moriya, A., Hashiba, Y., Inokuchi, Y., Kunii, Y., Kase, M.
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Technology (01.06.2007)
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Conference Proceeding
Novel Stack-SIN Gate Dielectrics for High Performance 30 nm CMOS for 45 nm Node with Uniaxial Strained Silicon
Ohta, H., Hori, M., Shima, M., Mori, H., Shimamune, Y., Sakuma, T., Hatada, A., Katakami, A., Kim, Y., Kawamura, K., Owada, T., Morioka, H., Watanabe, T., Hayami, Y., Ogura, J., Tamura, N., Kojima, M., Hashimoto, K.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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Conference Proceeding
High-Performance Low Operation Power Transistor for 45nm Node Universal Applications
Sugii, T., Hashimoto, K., Miyajima, M., Sato, S., Kojima, M., Nakai, S., Fukuyama, S., Nakaishi, M., Sukegawa, K., Aoyama, T., Tamura, N., Fukutome, H., Miyashita, T., Sakuma, T., Ota, H., Katakami, A., Shimamune, Y., Hatada, A., Minakata, H., Hayami, Y., Mori, T., Okoshi, K., Isome, T., Watanabe, T., Morioka, H., Kokura, H., Ogura, J., Sugimoto, K., Owada, T., Okuno, M., Pidin, S., Kawamura, K., Sakoda, T., Yamaguchi, A., Okabe, K., Shima, M.
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)
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Conference Proceeding
Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain
Kim, Y.S., Shimamune, Y., Fukuda, M., Katakami, A., Hatada, A., Kawamura, K., Ohta, H., Sakuma, T., Hayami, Y., Morioka, H., Ogura, J., Minami, T., Tamura, N., Mori, T., Kojima, M., Sukegawa, K., Hashimoto, K., Miyajima, M., Satoh, S., Sugii, T.
Published in 2006 International Electron Devices Meeting (01.12.2006)
Published in 2006 International Electron Devices Meeting (01.12.2006)
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Conference Proceeding
Cluster Ion Implantation for beyond 45nm node novel device applications
Tanjyo, M., Nagayama, T., Hamamoto, N., Umisedo, S., Koga, Y., Maehara, N., Matsumoto, T., Nagai, N., Ootsuka, F., Katakami, A., Shirai, K., Watanabe, T., Nakata, H., Kitajima, M., Aoyama, T., Eimori, T., Nara, Y., Ohji, Y., Saker, K., Krull, W., Jacobson, D., Horsky, T.
Published in Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08) (01.05.2008)
Published in Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08) (01.05.2008)
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Conference Proceeding
High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD
Ohta, H., Kim, Y., Shimamune, Y., Sakuma, T., Hatada, A., Katakami, A., Soeda, T., Kawamura, K., Kokura, H., Morioka, H., Watanabe, T., Hayami, J.O.Y., Ogura, J., Tajima, M., Mori, T., Tamura, N., Kojima, M., Hashimoto, K.
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
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Conference Proceeding
한,일 양국 신세대의 소비문화에 관한 비교연구
최석신(Soug Shin Choi), 이광배(Gwang Bae Lee), 가타가미히로시(Katakami Hiroshi)
Published in Asia Marketing Journal (Online) (2002)
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Published in Asia Marketing Journal (Online) (2002)
Journal Article