A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface
Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Get full text
Conference Proceeding