A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM
Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Fujimura, Y., Ando, K., Kusunoki, T., Yamaguchi, K., Homma, N.
Published in IEEE journal of solid-state circuits (01.11.1998)
Published in IEEE journal of solid-state circuits (01.11.1998)
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Journal Article
Ca intercalated bilayer graphene as a thinnest limit of superconducting C₆Ca
Kanetani, Kohei, Sugawara, Katsuaki, Sato, Takafumi, Shimizu, Ryota, Iwaya, Katsuya, Hitosugi, Taro, Takahashi, Takashi
Published in Proceedings of the National Academy of Sciences - PNAS (27.11.2012)
Published in Proceedings of the National Academy of Sciences - PNAS (27.11.2012)
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Journal Article
A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM
Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Kusunoki, T., Yamaguchi, K., Homma, N.
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
Published in 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) (1998)
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Conference Proceeding
Journal Article
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM
Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Nishiyama, M., Ohhata, K., Arakawa, F., Kusunoki, T., Yamaguchi, K., Hotta, A., Homma, N.
Published in IEEE journal of solid-state circuits (01.08.2000)
Published in IEEE journal of solid-state circuits (01.08.2000)
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Journal Article
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz
Ohhata, K., Arakawa, F., Kusunoki, T., Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Nishiyama, M., Yamaguchi, K., Homma, N., Hotta, A.
Published in IEEE journal of solid-state circuits (01.04.2000)
Published in IEEE journal of solid-state circuits (01.04.2000)
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Journal Article
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM
Nambu, H., Kanetani, K., Idei, Y., Masuda, T., Higeta, K., Ohayashi, M., Usami, M., Yamaguchi, K., Kikuchi, T., Ikeda, T., Ohhata, K., Kusunoki, T., Homma, N.
Published in IEEE journal of solid-state circuits (01.04.1995)
Published in IEEE journal of solid-state circuits (01.04.1995)
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Journal Article
Conference Proceeding
High-speed sensing techniques for ultrahigh-speed SRAMs
Nambu, H., Kanetani, K., Idei, Y., Homma, N., Yamaguchi, K., Hiramoto, T., Tamba, N., Odaka, M., Watanabe, K., Ikeda, T., Ohhata, K., Sakurai, Y.
Published in IEEE journal of solid-state circuits (01.04.1992)
Published in IEEE journal of solid-state circuits (01.04.1992)
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Journal Article
An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM
Yamaguchi, K., Nanbu, H., Kanetani, K., Homma, N., Nakamura, T., Ohhata, K., Uchida, A., Ogiue, K.
Published in IEEE journal of solid-state circuits (01.10.1989)
Published in IEEE journal of solid-state circuits (01.10.1989)
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Journal Article
Coexistence of multiple metastatic brain tumors from thyroid carcinoma and cerebral aneurysms
Yamamoto, F, Maruiwa, M, Kanetani, K, Matsuo, H, Shigemori, M, Kuramoto, S
Published in Nō shinkei geka (01.04.1990)
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Published in Nō shinkei geka (01.04.1990)
Journal Article
Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core
Suzuki, T., Nakahara, S., Iwahashi, S., Higeta, K., Kanetani, K., Nambu, H., Yoshida, M., Yamaguchi, K.
Published in 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) (2002)
Published in 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) (2002)
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Conference Proceeding
A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM
Homma, N., Yamaguchi, K., Nanbu, H., Kanetani, K., Nishioka, Y., Uchida, A., Ogiue, K.
Published in IEEE journal of solid-state circuits (01.10.1986)
Published in IEEE journal of solid-state circuits (01.10.1986)
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Journal Article
Attempt of intracranial IC bypass for giant aneurysm in the cavernous portion of the carotid artery
Honda, E, Hayashi, T, Ri, S, Kanetani, K, Oshima, Y, Utsunomiya, H, Honda, Y, Sato, Y, Fukushima, T
Published in Nō shinkei geka (01.04.1989)
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Published in Nō shinkei geka (01.04.1989)
Journal Article
A redundancy technique for ultra-high-speed SRAMs
Nambu, H., Kanetani, K., Idei, Y., Homma, N., Hiramoto, T., Tamba, N., Odaka, M., Watanabe, K., Ikeda, T., Ohhata, K., Sakurai, Y., Yamaguchi, K.
Published in Proceedings of the 1991 Bipolar Circuits and Technology Meeting (1991)
Published in Proceedings of the 1991 Bipolar Circuits and Technology Meeting (1991)
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Conference Proceeding
A case of Congenital Abscence of Right Main Pulmonary Artery
Awashima, Fumiyoshi, Kanetani, Kunio, Sunaga, Yoshinobu, Hoshino, Rinjiro, Kobayashi, Jiro, Kobayashi, Toshio, Kobayashi, Isao, Fueki, Ryuzo, Kobayashi, Setsuo, Henshiki, Atsuko
Published in Nihon Kyōbu Shikkan Gakkai zasshi (01.04.1976)
Published in Nihon Kyōbu Shikkan Gakkai zasshi (01.04.1976)
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Journal Article
On an ALOHA game with unknown selfish nodes
Sakakibara, K, Kanetani, K, Taketsugu, J
Published in 2010 10th International Symposium on Communications and Information Technologies (01.10.2010)
Published in 2010 10th International Symposium on Communications and Information Technologies (01.10.2010)
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Conference Proceeding
A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM
YAMAGUCHI, K, NAMBU, H, OHHATA, K, SAKURAI, Y, KANETANI, K, IDEI, Y, HOMMA, N, HIRAMOTO, T, TAMBA, N, WATANABE, K, ODAKA, M, IKEDA, T
Published in IEEE journal of solid-state circuits (01.02.1992)
Published in IEEE journal of solid-state circuits (01.02.1992)
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Journal Article