Baud rate pattern-adaptable dual loop clock recovery for high speed serial links
Malhotra, Gaurav, Kamali, Jalil, Amirkhany, Amir
Published in 2021 55th Asilomar Conference on Signals, Systems, and Computers (31.10.2021)
Published in 2021 55th Asilomar Conference on Signals, Systems, and Computers (31.10.2021)
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Conference Proceeding
BER analysis of high speed links with nonlinearity
Malhotra, Gaurav, Kamali, Jalil
Published in 2015 49th Asilomar Conference on Signals, Systems and Computers (01.11.2015)
Published in 2015 49th Asilomar Conference on Signals, Systems and Computers (01.11.2015)
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Conference Proceeding
Journal Article
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process
Jose, Anup, Abramzon, Valentin, Elzeftawi, Mohamed, Wang, Michael, Kim, Kyunglok, Song, Younghoon, Moballegh, Shiva, Kamali, Jalil, Amirkhany, Amir
Published in 2019 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2019)
Published in 2019 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2019)
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Conference Proceeding
METHOD FOR TRANSMITTING VIDEO AND DATA TRANSMITTER
GREGORY W. COOK, KAMALI JALIL, HAGHANI EHSAN, MOBASHER AMIN, ZAMORA DAVID
Year of Publication 05.04.2018
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Year of Publication 05.04.2018
Patent