SEMICONDUCTOR DEVICE
MIWA HITOSHI, ISHII KYOKO, KAWAHARA TAKAYUKI, HIGUCHI HISAYUKI, KITSUKAWA GORO
Year of Publication 30.06.1989
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Year of Publication 30.06.1989
Patent
Semiconductor integrated circuit device with internal voltage drop circuits
TAKAHASHI; TSUTOMU, MORINO; MAKOTO, UDO; SHINJI, TAKANO; MITSUHIRO, YOSHIOKA; HIROSHI, MIYATAKE; SHINICHI, ISHII; KYOKO
Year of Publication 02.08.1994
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Year of Publication 02.08.1994
Patent
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
TAKANO MITSUHIRO, MORINO MAKOTO, ISHII KYOKO, UDO SHINJI, YOSHIOKA HIROSHI, MIYATAKE SHINICHI, TAKAHASHI TSUTOMU
Year of Publication 14.09.1992
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Year of Publication 14.09.1992
Patent
Semiconductor integrated circuit device
TSUNOZAKI; MANABU, MIYATAKE; SINICHI, NOZAKI; KOICHI, MORINO; MAKOTO, HOSHIDA; AKIHIKO, UDO; SHINJI, YOSHIOKA; HIROSHI, KOYAMA; YOSHIHISA, AOYAGI; HIDETOMO, ISHII; KYOKO
Year of Publication 08.08.1995
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Year of Publication 08.08.1995
Patent
Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value compensated for external supply voltage variations
TSUNOZAKI; MANABU, HORIGUCHI; MASASHI, KAJIGAYA; KAZUHIKO, ETOH; JUN, AOKI; MASAKAZU, IKENAGA; SHIN'ICHI, UDAGAWA; TETSU, ITOH; KIYOO, ISHII; KYOKO, OSHIMA; KAZUYOSHI
Year of Publication 20.06.1995
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Year of Publication 20.06.1995
Patent
MEDICAMENTO ENCAPSULADO
SHIMOJO, FUMIO, HATA, TAKEHISA, KADO, KAZUTAKE, ISHII, KYOKO, SAWAI, SEIJI
Year of Publication 16.12.2001
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Year of Publication 16.12.2001
Patent
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
NOZAKI KOICHI, MORINO MAKOTO, AOYANAGI HIDETOMO, ISHII KYOKO, YOSHIOKA HIROSHI, KOYAMA YOSHIHISA, UDO SHINJI, HOSHIDA AKIHIKO, MIYATAKE SHINICHI, TSUNOSAKI MANABU
Year of Publication 11.03.1994
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Year of Publication 11.03.1994
Patent
TESTING METHOD FOR A SEMICONDUCTOR MEMORY DEVICE
YANAGISAWA, KAZUMASA, KATSUKAWA, KORO, OUJI, YOSHIAKI, NAKAMURA, MASAYUKI, NOZOE, ATSUSHI, MATSUMOTO, TETSURO, KOBAYASHI, YUTAKA, ISHII, KYOKO, MISASHI, WAZUO, KINOSHITA, YOSHITAKA, WADA, SHOJI, OTA, TATSUYUKI, UDAKAWA, TETSU, MIWA, HITOSHI, TSUKADA, HIROMI
Year of Publication 17.08.1998
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Year of Publication 17.08.1998
Patent
Encapsulated pharmaceutical composition
SHIMOJO, FUMIO, HATA, TAKEHISA, KADO, KAZUTAKE, ISHII, KYOKO, SAWAI, SEIJI
Year of Publication 11.06.1999
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Year of Publication 11.06.1999
Patent
A 23ns 1Mbit BiCMOS DRAM
Yanagisawa, Kazumasa, Kitsukawa, Goro, Kobayashi, Yutaka, Kinoshita, Yoshitaka, Ohta, Tatsuyuki, Udagawa, Tetsu, Ishii, Kyoko, Miwa, Hitoshi, Miyazawa, Hiroyuki, Ouchi, Yoshiaki, Tsukada, Hiromi, Matsumoto, Tetsuro, Itoh, Kiyoo
Published in ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference (01.09.1989)
Published in ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference (01.09.1989)
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Conference Proceeding
Dynamic Random Access Type Semiconductor Device
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 09.04.1996
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Year of Publication 09.04.1996
Patent
Testing method for a semiconductor memory device
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 04.01.1994
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Year of Publication 04.01.1994
Patent
Bi-CMOS semiconductor memory device, including improved layout structure and testing method
KOBAYASHI; YUTAKA, NOZOE; ATSUSHI, KINOSHITA; YOSHITAKA, TSUKADA; HIROMI, YANAGISAWA; KAZUMASA, NAKAMURA; MASAYUKI, OUCHI; YOSHIAKI, MIHASHI; KAZUO, ISHII; KYOKO, MATSUMOTO; TETSUROU, WADA; SHOJI, UDAGAWA; TETSU, OHTA; TATSUYUKI, MIWA; HITOSHI, KITSUKAWA; GORO
Year of Publication 22.09.1992
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Year of Publication 22.09.1992
Patent
RESISTANCE MEANS, LOGIC CIRCUIT, INPUT CIRCUIT, FUSE-BLOWING CIRCUIT, DRIVE CIRCUIT, POWER-SUPPLY CIRCUIT AND ELECTROSTATIC PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM, AND ITS LAYOUT SYSTEM AND TEST SYSTEM
TSUKADA AKIMI, OUCHI YOSHIAKI, KINOSHITA YOSHITAKA, OTA TATSUYUKI, ISHII KYOKO, NAKAMURA MASAYUKI, KOBAYASHI YUTAKA, UDAGAWA SATORU, MIHASHI KAZUO, WADA SHOJI, MIWA HITOSHI, NOZOE ATSUSHI, MATSUMOTO TETSUO, YANAGISAWA KAZUMASA, KITSUKAWA GORO
Year of Publication 01.10.1990
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Year of Publication 01.10.1990
Patent