Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Sunter, S., Yung-Fa Chou, Ding-Ming Kwai
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2013)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2013)
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Journal Article
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
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Conference Proceeding
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
YOU, Jhih-Wei, HUANG, Shi-Yu, LIN, Yu-Hsiang, TSAI, Meng-Hsiu, KWAI, Ding-Ming, CHOU, Yung-Fa, WU, Cheng-Wen
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
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Journal Article
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool
Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Schaefer, Andre, Cheng-Wen Wu
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.09.2014)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.09.2014)
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Journal Article
3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
Shen, Wen-Wei, Kao, Ming-Jer, Chen, Kuan-Neng, Lin, Yu-Min, Chen, Shang-Chun, Chang, Hsiang-Hung, Chang, Tao-Chih, Lo, Wei-Chung, Lin, Chien-Chung, Chou, Yung-Fa, Kwai, Ding-Ming
Published in IEEE journal of the Electron Devices Society (01.01.2018)
Published in IEEE journal of the Electron Devices Society (01.01.2018)
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Journal Article
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization
Yu, Cody Hao, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2014)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.05.2014)
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Journal Article
DLL-Assisted Clock Synchronization Method for Multi-Die ICs
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
Published in 2017 IEEE International Conference on Computer Design (ICCD) (01.11.2017)
Published in 2017 IEEE International Conference on Computer Design (ICCD) (01.11.2017)
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Conference Proceeding
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
Published in 2016 IEEE International Test Conference (ITC) (01.11.2016)
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Conference Proceeding
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 29th VLSI Test Symposium (01.05.2011)
Published in 29th VLSI Test Symposium (01.05.2011)
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Conference Proceeding
Small delay testing for TSVs in 3-D ICs
Huang, Shi-Yu, Lin, Yu-Hsiang, Tsai, Kun-Han (Hans), Cheng, Wu-Tung, Sunter, Stephen, Chou, Yung-Fa, Kwai, Ding-Ming
Published in DAC Design Automation Conference 2012 (03.06.2012)
Published in DAC Design Automation Conference 2012 (03.06.2012)
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Conference Proceeding
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs
Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
Published in 2017 International Test Conference in Asia (ITC-Asia) (01.09.2017)
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Conference Proceeding
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers
CHANG, Hsiu-Ming, HUANG, Jiun-Lang, KWAI, Ding-Ming, CHENG, Kwang-Ting, WU, Cheng-Wen
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2013)
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Journal Article
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
Published in 2010 19th IEEE Asian Test Symposium (01.12.2010)
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Conference Proceeding
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
Published in 2016 IEEE 25th Asian Test Symposium (ATS) (01.11.2016)
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Conference Proceeding
A unified formulation of honeycomb and diamond networks
Parhami, B., Ding-Ming Kwai
Published in IEEE transactions on parallel and distributed systems (01.01.2001)
Published in IEEE transactions on parallel and distributed systems (01.01.2001)
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Journal Article
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs
Yun-Chao Yu, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
Published in 2014 IEEE 23rd Asian Test Symposium (01.11.2014)
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Conference Proceeding